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hardware/software partitioning using Bayesian belief networks

IEEE TRANSACTIONS ON SYSTEMS MAN AND CYBERNETICS PART A-SYSTEMS AND HUMANS 2007年第5期37卷 655-668页

作者： Olson, John T. Rozenblit, Jerzy W. Talarico, Claudio Jacak, Witold IBM Inc Armonk NY 10504 USA Univ Arizona Dept Elect & Comp Engn Tucson AZ 85721 USA Eastern Washington Univ Dept Elect Engn Cheney WA 99044 USA Upper Austria Univ Appl Sci Dept Software Engn A-4232 Hagenberg Austria

In heterogeneous system design, partitioning of the functional specifications into hardware (HW) and software (SW) components is an important procedure. Often, an HW platform is chosen, and the SW is mapped onto the existing partial solution, or the actual partitioning is performed in an ad hoc manner. The partitioning approach presented here is novel in that it uses Bayesian belief networks (BBNs) to categorize functional components into HW and SW classifications. The BBN's ability to propagate evidence permits the effects of a classification decision that is made about one function to be felt throughout the entire network. In addition, because BBNs have a belief of hypotheses as their core, a quantitative measurement as to the correctness of a partitioning decision is achieved. A methodology for automatically generating the qualitative structural portion of BBN and the quantitative link matrices is given. A case study of a programmable thermostat is developed to illustrate the BBN approach. The outcomes of the partitioning process are discussed and placed in a larger design context, which is called model-based codesign.

关键词： hardware/software partitioning heterogenous system design model-based codesign

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hardware/software partitioning for Heterogenous MPSoC Considering Communication Overhead

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INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING 2017年第4期45卷 899-922页

作者： Ouyang, Aijia Peng, Xuyu Liu, Jing Sallam, Ahmed Zunyi Normal Coll Dept Informat Engn Zunyi 563002 Guizhou Peoples R China Wuhan Univ Sci & Technol Coll Comp Sci & Technol Wuhan 430065 Peoples R China Suez Canal Univ Fac Comp & Informat Ismailia Egypt

hardware/software partitioning (HSP) is an important step in the co-design of hardware/software. This paper addresses the problem of HSP with communication (HSPC) on heterogeneous multiprocessor system-on-chip (MPSoC). The classic HSP is modeled as an optimization problem with an objective of minimizing the finishing time in system under the hardware area constraints. First, we put forward an optimal method, integer linear programming (ILP) algorithm, for solving the problem for small inputs. Then, we propose two other algorithms using dynamic programming (DP) method, i.e., Optimal Tree partitioning (OTP) method for tree-structured graphs and Tree Cover partitioning (TCP) algorithm for general graphs in polynomial time. The overall performance of the proposed algorithms is evaluated through comparisons with that of a genetic algorithm (GA) and a greedy algorithm which are commonly used to solve HSP problem. We have conducted experimental performance evaluation on various benchmarks with different combinations of computation to communication ratios and hardware area constraints. The experimental results show that OTP algorithm can generate optimal solutions with much faster speed than ILP, and TCP algorithm can obtain near-optimum with higher quality than those produced by GA and greedy algorithm.

关键词： Communication Dynamic programming hardware/software partitioning Heuristic Integer linear programming

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hardware/software partitioning for multifunction systems

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1998年第9期17卷 819-837页

作者： Kalavade, A Subrahmanyam, PA AT&T Bell Labs Murray Hill NJ 07974 USA Stanford Univ Comp Syst Lab Stanford CA 94305 USA

We are interested in optimizing the design of multifunction embedded systems such as multistandard audio/video codecs and multisystem phones. Such systems run a prespecified set of applications, and any "one" of the applications is selected at a run time, depending on system parameters. Our goal is to develop a methodology for the efficient design of such systems, A key observation underlying our method is that it may not be efficient to design for each application separately, This is attributed to two factors. First, considering each application in isolation can lead to application-specific decisions that do not necessarily lead to the best overall system solution: Second, these applications typically tend to have several commonalities among them, and considering applications independently may lead to inconsistent mappings of common tasks in different applications, Our approach is to optimize jointly across the set of applications while ensuring that each application itself meets its timing constraints. Based on these guiding principles, we formulate, as a codesign problem, the design and synthesis of an efficient hardware-software implementation for a multifunction embedded system, The first step in our methodology is to identify nodes that represent similar functionality across different applications, Such "common" nodes are characterized by several metrics such as their repetitions, urgency, concurrency, and performance/area tradeoff. These metrics are quantified and used by a hardware/software partitioning tool to influence hardware/software mapping decisions. The idea behind this is to bias common tasks toward the same resource as far as possible while also considering preferences and timing constraints local to each application, Further, relative criticality of applications is also considered, and the mapping decisions in more critical applications are allowed to influence those in less critical applications. We demonstrate how this is achieved by modifying a

关键词： hardware-software codesign hardware/software partitioning multifunction systems system-level design video encode/decode

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hardware/software partitioning of embedded systems with multiple hardware processes

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IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES 1997年第5期144卷 285-294页

作者： Hendry, DC Sananikone, DS Univ Aberdeen Dept Engn Aberdeen AB9 2UE Scotland

COSYN is an hardware/software partitioning tool for embedded systems with multiple hardware processes. It produces a system hardware/software partition whilst satisfying system constraints, where feasible. COSYN uses a CIPN (coloured interpreted Petri net) to model systems, and to provide simulation data for the partitioning algorithm. The CIPN provides modelling capability for multiple processes and interprocess communication primitives. The partitioning algorithm, which adopts a fine-grained approach to system partitioning (it considers moving nodes at the basic block level), is based on selecting blocks based on their potential speedup and extra hardware requirements, using hardware and software execution time estimators. The interdependence between interprocess communication primitives is exploited to achieve a better hardware/software partition. Results for an input example pdi using different partitioning algorithms are given which illustrate the benefits of the approach presented in this paper.

关键词： embedded systems hardware/software partitioning electronic design automation

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hardware/software partitioning of Embedded System-on-Chip Applications 23

Hardware/Software Partitioning of Embedded System-on-Chip Ap...

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23rd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)

作者： Tang, Jia Wei Hau, Yuan Wen Marsono, M. N. Univ Teknol Malaysia Fac Elect Engn Johor Baharu Johor Malaysia Univ Teknol Malaysia Fac Biosci & Med Engn Johor Baharu Johor Malaysia

ISBN: (纸本)9781467391405

HW/SW partitioning is an important development step during HW/SW co-design to ensure application performance in embedded System-on-Chip (SoC). This paper formulates the optimization of HW/SW partitioning aiming at maximizing streaming throughput with predefined area constraint, targeted for multi-processor system with hardware accelerator sharing capability. Two software-oriented and the second hardware-oriented greedy heuristic algorithms for HW/SW partitioning are proposed and tested on several random graphs and one multimedia application (MP3 decoder). Results show that the best result from both proposed greedy algorithms produce 93.6% near-optimal solution compared to brute force ground truth with faster HW/SW partitioning time.

关键词： Embedded system hardware/software partitioning streaming applications

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hardware/software partitioning of software binaries 02

Hardware/software partitioning of software binaries

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International Conference on Computer-Aided Design

作者： Stitt, G Vahid, F Univ Calif Riverside Dept Comp Sci & Engn Riverside CA 92521 USA

ISBN: (纸本)0780376072

partitioning an embedded system application among a microprocessor and custom hardware has been shown to improve the performance, power or energy of numerous examples. The advent of single-chip microprocessor/FPGA platforms makes such partitioning even more attractive. Previous partitioning approaches have partitioned sequential program source code, such as C or C++. We introduce a new approach that partitions at the software binary level. Although source code partitioning is preferable from a purely technical viewpoint, binary-level partitioning provides several very practical benefits for commercial acceptance. We demonstrate that binary-level partitioning yields competitive speedup results compared to source-level partitioning, achieving an average speedup of 1.4 compared to 1.5 for eight benchmarks partitioned on a single-chip microprocessor/FPGA device.

关键词： hardware/software partitioning synthesis binary translation decompilation low power assembly language FPGA codesign synthesis

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hardware/software partitioning Algorithm for Embedded Systems with Repeated Functionalities

Hardware/Software Partitioning Algorithm for Embedded System...

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IEEE Region 10 Conference (TENCON 2008)

作者： Arunachalam, V. Sapra, Sunny Chaitanya, N. S. K. Raina, Jewan Prakash VIT Univ Sch Elect Sci Vellore 632014 Tamil Nadu India VIT Univ Sch Comp Sci Vellore 632014 Tamil Nadu India VIT Univ Ctr Nanotechnol Res Vellore 632014 Tamil Nadu India

ISBN: (纸本)9781424424085

hardware/software partitioning is a critical phase in the codesign approach of embedded system design. Most of the partitioning algorithms proposed assume that an embedded,system has distinct sub-modules. The issue of partitioning of resource constrained embedded systems consisting of multiple occurrences of a single functionality, needs to be addressed. In this paper, we propose a Genetic Algorithm (GA) based partitioning algorithm which addresses the utilization of the already existing hardware instances on the chip for the repeated functionalities of the system, based on the constraints and concurrency of the functionalities.

关键词： embedded systems hardware/software co-design hardware/software partitioning genetic algorithm

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hardware/software partitioning and scheduling algorithm based on FPGA 7

Hardware/software partitioning and scheduling algorithm base...

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7th International Conference Control Automation (CA 2014)

作者： Li, Lanying Chen, Longjuan Harbin Univ Sci & Technol Coll Comp Sci & Technol Harbin 150080 Peoples R China

ISBN: (纸本)9781479982066

For low power consumption of system structure in embedded heterogeneous multi-core processor, decompose the hardware/software partitioning into task partitioning and low power scheduling in two stages. The algorithm of reducing power consumption is adopted at each stage, and finally optimal algorithm of two stages will be integrated in order to achieve the system goal of maximum reduction of the power consumption.

关键词： low power consumption heterogeneous multi-core processor hardware/software partitioning

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hardware/software partitioning for platform-based design method 05

Hardware/software partitioning for platform-based design met...

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10th Asia and South Pacific Design Automation Conference

作者： Xiong, Zhihui Chen, Jihua Li, Sikun Univ Def Technol Sch Comp Sci Changsha 410073 Peoples R China

ISBN: (纸本)0780387368

Ant System Algorithm has the advantages of positive feedback and efficient convergence in optimal searching, but it lacks initial pheromone, which greatly limits this algorithm's searching speed. Oriented to Platform-Based Design of System-on-a-Chip, we present a hardware/software bi-partitioning algorithm based on Ant System Algorithm with Initial Pheromone. The main ideas are: a). Reuse the partitioning result. of reference design provided by Platform-Based Design method as current design's initial partitioning, which is then converted into the initial pheromone needed by Ant System Algorithm. b). Search for the optimal partitioning scheme with the Ant System Algorithm based on the initial pheromone. Our algorithm adopts system level reusing feature of Platform-Based Design method to prevent the disadvantages of Ant System Algorithm. Experiments show our algorithm-improves the efficiency of Ant System Algorithm by an average of forty percent.

关键词： system-on-chip logic partitioning software reusability hardware-software codesign hardware/software partitioning platform-based design method Ant system algorithm positive feedback efficient convergence optimal searching initial pheromone system-on-a-chip reference design optimal partitioning system level reusing

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hardware/software partitioning in Embedded System Based on Novel United Evolutionary Algorithm Scheme

Hardware/Software Partitioning in Embedded System Based on N...

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International Conference on Computer and Electrical Engineering

作者： Tong, Qiaoling Zou, Xuecheng Tong, Hengqing Gao, Fei Zhang, Qiao Huazhong Univ Sci & Technol Dept Elect Sci & Technol Wuhan Peoples R China Wuhan Univ Technol Dept Mat Wuhan Peoples R China

ISBN: (纸本)9780769535043

hardware/software partitioning is a key problem in hardware/software, co-design and global optimums detection of the objective function is of vital importance in hardware/software partitioning. Though stochastic optimization strategies simulating evolution process are proved to be valuable tools, the balance between exploitation and exploration of which is difficult to be maintained In this paper, the model of the embedded system was constructed by directed acyclic graph to obtain the objective function. Then some established techniques to improve the performance of evolutionary computation are discussed, such as uniform design, deflection and stretching the objective function, and space contraction. A novel scheme of evolutionary algorithms is proposed to solve the optimization problems through adding evolution operations to the searching space contracted regularly with these techniques. A typical evolutionary algorithm differential evolution is chosen to exhibit the performance of new scheme. The improved algorithm can avoid local optimal solution efficiently and be conveniently implemented in the field of hardware/software partitioning.

关键词： Evolutionary Algorithm hardware/software partitioning

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