In this paper we derive delay and transition time macromodels for GaAs DCFL logic gates. The macromodels are derived by a systematic application of dimensional analysis aimed at Ending suitable minimal functional form...
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In this paper we derive delay and transition time macromodels for GaAs DCFL logic gates. The macromodels are derived by a systematic application of dimensional analysis aimed at Ending suitable minimal functional forms that capture the effects of all relevant parameters. The process is illustrated through a detailed step-by-step account of the macromodel development for DCFL inverters. Based on different modeling approximations, one- and two-argument macromodel functions are derived and compared. The inverter macromodel is then used as a basis for developing timing macromodels for superbuffers and NOR gates. The NOR gate macromodels account for the simultaneous and near-simultaneous switching of two inputs, with an extension to multiple inputs.
The general problem of analysis of an asynchronous logic circuit was formulated in earlier work where the general methods of solution of its main subproblems were considered. The present paper is a continuation of the...
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The general problem of analysis of an asynchronous logic circuit was formulated in earlier work where the general methods of solution of its main subproblems were considered. The present paper is a continuation of the study of particular cases. Different kinds of hazard analysis problems are considered. The superposition of functions is utilised as one of the basic dimension reducing transformations. Analysis by parts is considered as a way of simplifying the computation of the domain. The domain of the analysis is restricted and the existence of critical classes in a given domain are determined.
It is known that circuit delays and timing skews in input vector changes influence choice of tests to detect delay faults. Tests for stuck-open faults in CMOS logic circuits can also be invalidated by circuit delays a...
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It is known that circuit delays and timing skews in input vector changes influence choice of tests to detect delay faults. Tests for stuck-open faults in CMOS logic circuits can also be invalidated by circuit delays and timing skews in input vector changes. Tests that detect modeled faults independent of the delays in the circuit under test are called robust tests. In this paper we propose an integrated approach to the design of combinational logic circuits in which all path delay faults and multiple line stuck-at, transistor stuck-open faults are detectable by robust tests. We also demonstrate that the proposed method guarantees the design of CMOS logic circuits in which all path delay faults are locatable.
Various full-swing BiCMOS logic circuits with complementary emitter-follower driver configuration are described. The performance of the circuits has been demonstrated in a 1.2-mu-m complementary BiCMOS technology with...
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Various full-swing BiCMOS logic circuits with complementary emitter-follower driver configuration are described. The performance of the circuits has been demonstrated in a 1.2-mu-m complementary BiCMOS technology with a 6-GHz n-p-n and a 2-GHz p-n-p transistor. For the basic circuit, gate delay (fan-in = 2, fan-out = 1) is 366 ps and driving capability is 288 ps/pF at 4 V. Delay-power trade-offs that depend on characteristics of the clamping diode between two base nodes of the complementary emitter-follower driver, parasitic capacitances at the two base nodes, and the technique used to achieve full swing have been identified for these circuits. These circuits show leverage over the conventional BiCMOS circuit for reduced power-supply voltages.
The iMemComp is a family of logic gates based on RRAM devices. It has potential advantage on the design of high-performance logic circuits, since the NAND, AND, NOT and transmission iMemComp gates only consume single ...
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The iMemComp is a family of logic gates based on RRAM devices. It has potential advantage on the design of high-performance logic circuits, since the NAND, AND, NOT and transmission iMemComp gates only consume single cycle, respectively. However, the synthesis method of logic circuits based on the iMemComp gates has not been systematically studied before. This work proposes the synthesis method of the row-oriented logic circuits based on the multi-input single-cycle iMemComp gates. The synthesis results show that the circuits generated from the proposed method outperform most of those RRAM based counterparts generated from the previous methods. Furthermore, the synthesis method of the array-oriented iMemComp logic circuits is proposed. The proposed array-oriented method generates the relatively high-performance logic circuits since both the row-based and the column-based single-cycle iMemComp gates are applied, and the generated circuits are relatively area-efficient because the intra-row and inter-row redundancies are utilized in the circuit mapping.
A novel structure of high-speed Josephson logic circuits is proposed. Josephson logic gates have latching characteristics and can hold data as long as bias currents are supplied. Through effective use of these latchin...
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A novel structure of high-speed Josephson logic circuits is proposed. Josephson logic gates have latching characteristics and can hold data as long as bias currents are supplied. Through effective use of these latching characteristics, logic circuits can be constructed with wide operating margins. Dual power supplies, properly phased, separately drive logic circuits divided into two groups. logic signals are transferred from one logic group to the other or vice versa, and one group is reset into a zero voltage state when the other group is active for logic operation. For combinational circuits, the basic configuration of an astable flip-flop and a delay circuit are presented to prevent the logic circuit from `racing'. As an example of sequential circuits, a bistable flip-flop to store data is constructed without any superconducting loop.
We present the phase-mode circuits based on new fabrication process elements for high-density circuit integration. Nb/AlNx/Nb overdamped junctions without external resistive shunts are applied to the phase-mode circui...
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We present the phase-mode circuits based on new fabrication process elements for high-density circuit integration. Nb/AlNx/Nb overdamped junctions without external resistive shunts are applied to the phase-mode circuits. The area of a bias feed resistor can be reduced by a replacement of the metallic resistor by the junction normal resistance. As a miniaturization method of an inductance, the effective inductance of a Josephson junction is used. The phase-mode circuits based on these new integration methods have been fabricated by Nb integration technology. Various aspects which are brought about by these fabrication technologies are discussed.
A model of a super pass gate (SPG) is adapted to allow multiple-valued logic circuit connections and designs that are normally prohibited by the formal synthesis and minimisation technique for the: device. The modific...
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A model of a super pass gate (SPG) is adapted to allow multiple-valued logic circuit connections and designs that are normally prohibited by the formal synthesis and minimisation technique for the: device. The modification of the SPG allows more efficient circuit minimisation to be achieved for functions that do not readily reduce under the formal synthesis technique.
This paper studies single-fault fault collapsing in sequential logic circuits. Two major phenomena, self-hiding (SH) and delayed reconvergence (DR), which arise from the existence of feedback paths and storage element...
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This paper studies single-fault fault collapsing in sequential logic circuits. Two major phenomena, self-hiding (SH) and delayed reconvergence (DR), which arise from the existence of feedback paths and storage elements in sequential circuits, are analyzed and found to cause the dominance relationship which is valid in combinational circuits but no longer valid in sequential circuits. A fault-collapsing procedure is proposed to collapse faults in sequential circuits. It first collapses faults in the non-SAD (self-hiding and delayed-reconvergence) gates of the combinational part of the sequential circuit and then further collapses faults by identifying the prime fan-out branches. Finally, it collapses faults in feedback lines. The collapsed faults constitute a sufficient representative set of prime faults. This procedure has been applied to collapse faults for 31 benchmark sequential circuits [1] and the number of faults has collapsed to 43% of the original number.
Aphysics-based compact model for III-V FETs is developed for logic circuit applications. The model is applied to study sub-22-nm technology 6T-SRAM cells with InGaAs MOSFETs. The pull-down and pass gate combination is...
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Aphysics-based compact model for III-V FETs is developed for logic circuit applications. The model is applied to study sub-22-nm technology 6T-SRAM cells with InGaAs MOSFETs. The pull-down and pass gate combination is optimized for maximum cell stability. The drawbacks of having a weak III-V PMOS as the pull-up device in a SRAM cell are investigated. In this letter, we propose a minimum requirement for PMOS strength for all-III-V SRAM to be viable in a logic chip. Also, by assuming a high-performance PMOS, we observe a 26% higher static current noise margin and a two times faster write speed compared to conventional SRAM.
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