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Multi-output majority gate-based design optimization by using evolutionary algorithm

SWARM AND EVOLUTIONARY COMPUTATION 2013年 10卷 25-30页

作者： Tehrani, Mohammad A. Navi, Keivan Kia-kojoori, Ali Shahid Beheshti Univ GC Nanotechnol & Quantum Comp Lab Tehran Iran Univ Calif Irvine Elect & Comp Engn Irvine CA 92714 USA

In this paper, a novel efficient method for optimizing multi-output majority gate based designs is proposed. Majority gate is a fundamental Boolean operator in some nano-scale technologies such as quantum-dot cellular automata (QCA). As a result, the design optimization must be directly implemented on majority gates instead of optimizing the design for AND-OR gates. In some other nanotechnologies, a fundamental element is Minority gate which could be simply converted to majority gate by the De Morgan's theorem. Here, the proposed optimization method works on the basis of evolutionary computation and can reduce both the number of majority gates and the worst-case delay of the circuit. The method is compared to some other optimization algorithms and its efficiency is verified. (C) 2013 Elsevier B.V. All rights reserved.

关键词： Quantum-dot cellular automata Majority gate logic optimization Evolutionary algorithm

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Area and speed oriented synthesis of FSMs for PAL-based CPLDs

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MICROPROCESSORS AND MICROSYSTEMS 2012年第1期36卷 45-61页

作者： Czerwinski, R. Kania, D. Silesian Tech Univ Inst Elect PL-44100 Gliwice Poland

New two-step methods of FSMs synthesis for PAL-based CPLDs are presented in the paper. The methods strive to find the optimum fit for a FSM to the structure of CPLD and aim at area and speed optimization. The first step for both methods is original state assignment that includes: techniques of two-level minimization, the limited number of terms contained in the cell and elements of adjusting to the logic optimization. The second step in the method oriented toward area minimization is PAL-oriented multi-level optimization, which is a search for implicants that can be shared by several functions. The second step in the method oriented toward speed maximization is based on utilizing tri-state buffers, thus enabling achievement of a one-logic-level output block. (C) 2011 Elsevier B.V. All rights reserved.

关键词： logic synthesis FSM State assignment logic optimization CPLD

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Block Permutations in Boolean Space to Minimize TCAM for Packet Classification

Block Permutations in Boolean Space to Minimize TCAM for Pac...

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IEEE INFOCOM Conference

作者： Wei, Rihua Xu, Yang Chao, H. Jonathan NYU Polytech Inst Dept ECE New York NY 10003 USA

ISBN: (纸本)9781467307758

Packet classification is one of the major challenges in designing high-speed routers and firewalls as it involves sophisticated multi-dimensional searching. Ternary Content Addressable Memory (TCAM) has been widely used to implement packet classification thanks to its parallel search capability and constant processing speed. However, TCAM-based packet classification has the well-known range expansion problem, resulting in a huge waste of TCAM entries. In this paper, we propose a novel technique called Block Permutation (BP) to compress the packet classification rules stored in TCAMs. The compression is achieved by performing block-based permutations on the rules represented in Boolean Space. We develop an efficient heuristic approach to find the permutations for compression and design its hardware implementation. Experiments on ClassBench classifiers and ISP classifiers show that the proposed BP technique can reduce TCAM entries by 53.99% on average.

关键词： Packet Classification TCAM Range Expansion Classifier Minimization logic optimization

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Identification of Threshold Functions and Synthesis of Threshold Networks

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2011年第5期30卷 665-677页

作者： Gowda, Tejaswi Vrudhula, Sarma Kulkarni, Niranjan Berezowski, Krzysztof Arizona State Univ Dept Comp Sci & Engn Tempe AZ 85281 USA Wroclaw Univ Technol Inst Comp Engn Control & Robot PL-50317 Wroclaw Poland

This paper presents a new and efficient heuristic procedure for determining whether or not a given Boolean function is a threshold function, when the Boolean function is given in the form of a decision diagram. The decision diagram based method is significantly different from earlier methods that are based on solving linear inequalities in Boolean variables that derived from truth tables. This method's success depends on the ordering of the variables in the binary decision diagram (BDD). An alternative data structure, and one that is more compact than a BDD, called a max literal factor tree (MLFT) is introduced. An MLFT is a particular type of factoring tree and was found to be more efficient than a BDD for identifying threshold functions. The threshold identification procedure is applied to the MCNC benchmark circuits to synthesize threshold gate networks.

关键词： Binary decision diagrams Boolean algebra Boolean function logic design logic optimization logic synthesis threshold function threshold logic

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Reed-Muller function optimization techniques with onset table

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Journal of Zhejiang University-Science C(Computers and Electronics) 2011年第4期12卷 288-296页

作者： Lun-yao WANG Yin-shui XIA Xie-xiong CHEN A. E. A. ALMAINI Department of Information Science and Electronic Engineering Zhejiang University Hangzhou 310027 China Faculty of Information Science and Engineering Ningbo University Ningbo 315211 China School of Engineering Napier University Edinburgh EH10 5DT UK

By mapping a fixed polarity Reed-Muller (RM) expression into an onset table and studying the properties of the onset table,an algorithm is proposed to obtain a compact multi-level single-output mixed-polarity RM function by searching for and extracting the common variables using the onset ***,by employing the multiplexer model,the algorithm is extended to optimize multi-level multi-output mixed-polarity RM *** proposed algorithm is implemented in C language and tested using some MCNC *** results show that the proposed algorithm can obtain a more compact RM form than that under fixed *** with published results,the proposed algorithm makes a significant speed improvement,with a small increase in the number of literals.

关键词： logic optimization Reed-Muller functions Multi-level Mixed polarity Onset table

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Research on Multi-valued Multi-input Multi-output logic Functions optimization Algorithm

Research on Multi-valued Multi-input Multi-output Logic Func...

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2008年国际电子商务、工程及科学领域的分布式计算和应用学术研讨会

作者： Qiu Jianlin Li Feng Chen Jianping Gu Xiang He Peng School of Computer Science and Technology,Nantong University,Nantong,Jiangsu 226019,P.R.China

In this paper,we make an approach to the logic optimization algorithm including two-valued logic optimization algorithm and multi-valued logic optimization algorithm,then present the algorithm to calculate essential prime cube and special relative redundancy cube and construct two-valued logic *** discuss the algorithm converting two-valued logic into multi-valued logic on the basis of building an assignment graph and present multi-valued logic optimization algorithm,we analyze and study logic function mini-covering based on studying the relevant theory of the multi-valued logic optimization which including the identification of judging macrocosm,the identification of essential prime implicants and relative redundancy and absolute redundancy implicants,and so *** design and realize a software system on logic optimization in programming language C. It overpasses testing of Benchmark and fight validate and it shows that the function of the software system on logic optimization is perfect and the optimization efficiency is so high viaw testing.

关键词： logic optimization Algorithm Two-valued logic Multi-valued logic Mini-covering

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XCS Cannot Learn All Boolean Functions 11

XCS Cannot Learn All Boolean Functions

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13th Annual Genetic and Evolutionary Computation Conference (GECCO)

作者： Ioannides, Charalambos Barrett, Geoff Eder, Kerstin Univ Bristol Ind Doctorate Ctr Syst Queens BldgUniv Walk Bristol BS8 1TR Avon England Broadcom Corp Broadcom BBE BU Bristol BS16 1FJ Avon England Univ Bristol Dept Comp Sci Bristol BS8 1UB Avon England

ISBN: (纸本)9781450305570

In this paper we applied the eXtended Classifier System (XCS) on a novel real world problem, namely digital Design Verification (DV). We witnessed the inadequacy of XCS on binary problems that contain high overlap between optimal rules especially when the focus is on population and not system level performance. The literature attempts to underplay the importance of the aforementioned weakness and in short, supports that a) XCS can potentially learn any Boolean function given enough resources are allocated (right parameters used) and b) the main metric deciding the learning difficulty of a Boolean function is the amount of classifiers required to represent it (i.e. vertical bar[O]vertical bar). With this work we experimentally refuted the aforementioned propositions and as a result of the work, we introduce new insights on the behavior of XCS when solving two-valued Boolean functions using a binary reward scheme (1000/0). We also introduce a new population metric (%[EPI]) that should necessarily be used to guide future research on improving XCS performance on the aforementioned problems.

关键词： Learning Classifier Systems (LCS) XCS logic optimization

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Optimized design of Parallel Prefix Ling Adder

Optimized design of Parallel Prefix Ling Adder

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IEEE International Conference on Electronics, Communications and Control (ICECC)

作者： Wang, Dayu Cui, Xiaoping Wang, Xiaojing Nanjing Univ Aeronaut & Astronaut Coll Elect & Informat Engn Nanjing Jiangsu Peoples R China

ISBN: (纸本)9781457703218

Parallel-prefix computation provides a highly efficient solution to binary addition problem. This paper proposes an advanced design based on parallel-prefix Ling adder. In order to further improve the Ling adder's performance, the preprocessing block and carry propagation block are all optimized to reduce the delay path for sum generation. Experimental results indicate that the proposed adder has an improvement of 21 percent time delay and 25 percent area compared to the traditional Ling adders.

关键词： parallel-prefix algorithm Ling adder logic optimization VLSI design

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Extended Sequential logic for Synchronous Circuit optimization and Its Applications

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2009年第4期28卷 469-477页

作者： Meher, Pramod Kumar Inst Infocomm Res Singapore 138632 Singapore

In this paper, we present a new approach for the extension of sequential logic functionality of D Hip-flop in order to perform an additional Boolean function simultaneously along with Its usual bit-storage function. We show that a combinational function of the form (a . b), (a + b), (a + (b) over bar), or ((a) over bar . b) which occurs frequently in a feedforward path with a D flip-flop could be implemented efficiently by a D flip-flop with RESET or SET provision. Similarly, (a circle plus b) or ((a . b) circle plus c) In the feedback loop with a D flip-flop could he implemented by a T flip-flop by suitable modification of the clock. The use of such extended Sequential logic is found to result in a significant reduction in critical path and saving in area complexity over the direct implementation. Moreover, we present a simple approach for the construction of CMOS T flip-flop by modification of clock signal of D flip-flop, which is found to be more efficient than the T flip-flop derived from JK flip-flop. The extended sequential logic is used for the implementation of finite-field multiplication over GF(2(m)) and carry-save addition of real numbers. In both these cases, the use of extended logic is found to offer a substantial saving in area and time complexity over the conventional implementations.

关键词： Carry-save addition combinational logic digital arithmetic finite-field arithmetic logic optimization sequential logic

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DECOMPOSITION-BASED logic SYNTHESIS FOR PAL-BASED CPLDs

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INTERNATIONAL JOURNAL OF APPLIED MATHEMATICS AND COMPUTER SCIENCE 2010年第2期20卷 367-384页

作者： Opara, Adam Kania, Dariusz Silesian Tech Univ Inst Comp Sci PL-44100 Gliwice Poland Silesian Tech Univ Inst Elect PL-44100 Gliwice Poland

The paper presents one concept of decomposition methods dedicated to PAL-based CPLDs. The proposed approach is an alternative to the classical one, which is based on two-level minimization of separate single-output functions. The key idea of the algorithm is to search for free blocks that could be implemented in PAL-based logic blocks containing a limited number of product terms. In order to better exploit the number of product terms, two-stage decomposition and BDD-based decomposition are to be used. In BDD-based decomposition methods, functions are represented by Reduced Ordered Binary Decision Diagrams (ROBDDs). The results of experiments prove that the proposed solution is more effective, in terms of the usage of programmable device resources, compared with the classical ones.

关键词： decomposition technology mapping logic optimization BDD CPLD

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