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Boolean logic Function Realized by Phase-Change Blade Type Random Access Memory

IEEE TRANSACTIONS ON ELECTRON DEVICES 2022年第4期69卷 1849-1857页

作者： Lian, Xiaojuan Wang, Lei Nanjing Univ Posts & Telecommunt Dept Microelect Coll Integrated Circuit Sci & Engn Nanjing 210023 Peoples R China Nanjing Univ Posts & Telecommunt Natl & Local Joint Engn Lab RF Integrat & Microas Nanjing 210023 Peoples R China

Phase-change random access memory (PCRAM) has been considered as one of the most promising candidates for future nonvolatile storage applications. Recent advent of the blade-type PCRAM further shed a light on its commercial prospect due to its much smaller energy consumption than the conventional Lance-type PCRAM. However, the logic computing capability of the blade-type PCRAM remains vague up-to-date. To deeply study its function versatility, we developed a comprehensive three-dimensional model based on the classical nucleation-growth theory to mimic the crystallization and amorphization processes of the blade-type PCRAM device. According to this well-established model, the device resistance after phase transformation was calculated with respect to different crystallization and amorphization pulses. By pertaining high and low pulse magnitudes and device resistances to appropriate input and output logic levels, a variety of Boolean logic functions, including ``nand,'' nor,'' and,'' or,'' and ``not,'' were successfully achieved on one single PCRAM cell. The feasibility of simultaneously realizing storage and logic computing functions on the designed PCRAM device was therefore demonstrated. Such intriguing merit, combined with its superb storage traits, makes the proposed blade-type PCRAM cell suitable for current in-memory computing and neuromorphic circuits as the key components of future digital computers operated on non-von Neumann mode.

关键词： Phase change random access memory Computational modeling Random access memory Mathematical models Crystallization logic functions logic devices Memory technologies memory used as logic models of computations optimization

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TVD-PB logic circuit based on camouflaging circuit for IoT security

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IET CIRCUITS DEVICES & SYSTEMS 2022年第1期16卷 40-52页

作者： Zhang, Yuejun Wu, Qiufeng Wang, Pengjun Wen, Liang Luan, Zhicun Gu, Chongyan Ningbo Univ Fac Elect Engn & Comp Sci Ningbo Zhejiang Peoples R China Wenzhou Univ Coll Elect & Elect Engn Wenzhou 325035 Peoples R China China Coast Guard Acad Dept Elect Technol Ningbo Zhejiang Peoples R China Queens Univ Belfast Inst Elect Commun & Informat Technol Ctr Secure Informat Technol Belfast Antrim North Ireland

Internet of Things (IoT) devices are vulnerable to many physical attacks, including reverse engineering and side-channel analysis because the sensitive information of circuits may be leaked through the physical characteristics of the device. A logic camouflaging circuit is proposed that uses a balanced power consumption and threshold voltage-defined technique to provide an antiphysical attack scheme to protect the hardware security for IoT devices. The proposed circuit uses a symmetric differential pull-down network in implementing the different logic functions through the threshold voltage reconfiguration circuit. As a result, the power consumption of the circuit attains balance and stability between two different logical operations. The proposed threshold voltage-defined power-balance (TVD-PB) design is fabricated using a 65-nm CMOS technology, and the core area occupies approximately 0.0044 mm(2), composed of NAND, NOR, XOR, and INV components and multiplier gates of the proposed TVD-PB circuit. The entire chip passed the logic function tests. The measured results show that the average similarity of the TVD-PB universal gate is 99.68%. In addition, the current margin is higher than 55 mu A and power consumption of 0.455 mW during each clock cycle at 1.2 V derives 0.1072% of the normalized energy deviation and 0.0453% of the normalized standard deviation. Compared with other state-of-the-art techniques, the power dependency against power attacks is improved effectively.

关键词： Internet of Things devices power attacks logic gates IoT devices logic functions physical attacks logic camouflaging circuit threshold voltage-defined technique IoT security power 0.455 mW TVD-PB logic circuit size 65 nm threshold voltage-defined power-balance symmetric differential pull-down network TVD-PB universal gate logic design side-channel analysis threshold voltage reconfiguration circuit security threshold logic Internet of Things integrated circuit design antiphysical attack scheme power consumption logical operations voltage 1.2 V circuit stability TVD-PB design reverse engineering hardware security power dependency circuit balance CMOS logic circuits logic function tests

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Multifunctional Optoelectronic Synapse Based on Ferroelectric Van der Waals Heterostructure for Emulating the Entire Human Visual System

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ADVANCED FUNCTIONAL MATERIALS 2022年第6期32卷 2108014-2108014页

作者： Guo, Feng Song, Menglin Wong, Man-Chung Ding, Ran Io, Weng Fu Pang, Sin-Yi Jie, Wenjing Hao, Jianhua Hong Kong Polytech Univ Dept Appl Phys Hung Hom Kowloon Hong Kong 999077 Peoples R China Sichuan Normal Univ Coll Chem & Mat Sci Chengdu 610066 Peoples R China

The development of optoelectronic synapses can provide an important breakthrough toward creating a sophisticated and adaptable artificial visual system analogous to that of humans. However, it remains a great challenge to implement the various functions of the biological visual neuromorphic system at the single device level. Intriguingly, 2D van der Waals (vdW) heterostructure may offer a platform to address the issue. Here, a novel multifunctional synaptic device based on ferroelectric alpha-In2Se3/GaSe vdW heterojunction is proposed to emulate the entire biological visual system. Essential synaptic behaviors are observed in response to light and electrical stimuli;additionally, the retina-like selectivity for light wavelengths and the achievement of Pavlov's dog experiment demonstrate the device's capacity for processing complex electrical and optical inputs. Beyond the optoelectronic synaptic behaviors, the device incorporates memory and logic functions analogous to those in the brain's visual cortex. The results of artificial neural network simulations show that the vdW heterojunction-based device is completely capable of performing logic operations and recognizing images with a high degree of accuracy. The study indicates that versatile devices with a rationally designed construction have great potential for efficiently processing complex visual information and may simplify the design of artificial visual systems.

关键词： artificial visual systems ferroelectric 2D materials logic functions memory optoelectronic synapses van der Waals heterostructures

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Technology Development and Modeling of Switching Lattices Using Square and H Shaped Four-Terminal Switches

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IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING 2022年第1期10卷 351-360页

作者： Akkan, Nihat Safaltn, Serzat Aksoy, Levent Cevik, Ismail Sedef, Herman Moritz, Csaba A. Altun, Mustafa Yildiz Tech Univ Elect & Commun Engn Dept TR-34220 Istanbul Turkey Istanbul Tech Univ Met & Mat Engn Dept TR-34469 Istanbul Turkey Istanbul Tech Univ Elect & Commun Engn Dept TR-34469 Istanbul Turkey Univ Massachusetts Elect & Comp Engn Dept Amherst MA 01003 USA

Switching lattices formed by four-terminal switches are introduced as dense rectangular structures to implement Boolean logic functions. It is clearly shown in literature by a variety of logic synthesis algorithms including the exact one, realizing logic functions on lattices with the fewest number of four-terminal switches, as well as the heuristic ones, that switching lattices offer a significant area advantage in terms of the number of switches over the conventional CMOS implementations. Although the computing potential of switching lattices has been well justified, the same thing cannot be said for their physical implementation. There have been conceptual ideas for the technology development of switching lattices, but no concrete and directly applicable technology has been proposed yet. In this study, we show that switching lattices can be implemented using the CMOS technology. For this purpose, we propose two different four-terminal switch structures with square and H shaped gates. We construct these two structures in three dimensional technology computer-aided design (TCAD) environment satisfying the design rules of the TSMC 65 nm CMOS process and perform simulations. Then, we develop Level 3 DC and AC models of these four-terminal switches in LTspice environment using the TCAD simulation data. As an experiment, we realize logic functions with the developed models using static and dynamic logic solutions. Experimental results show that the realization of logic functions using switching lattices occupy much less layout area and have competitive delay and power consumption values when compared to the conventional CMOS implementations.

关键词： Lattices logic gates Semiconductor device modeling Switches logic functions Computational modeling Electrodes Emerging technologies four-terminal switch switching lattice technology simulation device modeling

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Minimal Realizations of logic functions Using Truth Table Method with Distributed Simplification

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IETE Journal of Education 2014年第1期55卷 26-32页

ABSTRACTABSTRACTIn the conventional method, a truth table (TT) is prepared from the specified logic function. Then it is expressed as the sum of min terms corresponding to the rows in which 1 appears. Finally, this function is further reduced using the Boolean identities. Thus, all the simplifications are concentrated at one place after the TT. This procedure does not always lead to the minimal realization. This paper deals with the minimal realization of logic function using TT in which TT is reduced successively by one variable at a time till all the variables are exhausted. The simplification is carried out, instead at the end of the truth table, at the end of each step of TT reduction. The method is shown to be systematic, and definitely leads to the minimal function. It is simpler in operation than that based on only Boolean identities, Karnaugh map and Quine-McClusky methods, and can handle any number of variables. It is explained with several examples. It is worth introducing as an improvement over the classical TT method in class room teaching.

关键词： Minimal realizations logic functions Truth table method Digital circuits

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Optimized Synthesis Method for Ultra-Low Power Multi-Input Material Implication logic With Emerging Non-Volatile Memories

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2021年第11期68卷 4433-4443页

作者： Puglisi, Francesco Maria Zanotti, Tommaso Pavan, Paolo Univ Modena & Reggio Emilia Dipartimento Ingn Enzo Ferrari I-41125 Modena Italy

In this paper, we revisit Boole's expansion theorem to propose a new synthesis method for implication logic circuits based on memristors. By rewriting the sum-of-products form of Boole's expansion theorem in terms that are best suited for the implication logic, we develop a generalized rule to derive the sequence of operations needed to realize any logic function written in the classical AND-OR form. The proposed method leverages on multi-input operation, minimizing both the number of steps required to compute a given Boolean function and the number of memristors involved. Moreover, it allows using well-established methods of logic circuit optimization like binary decision diagrams, Karnaugh maps, and heuristic algorithms, that are already implemented in commercial CAD software. The proposed method allows a fair comparison between the performance of CMOS and implication logic implementations of the same logic function under the same degree of optimization, and is shown to outperform existing approaches. Possible device-circuit co-design strategies to optimize circuit performance are finally discussed.

关键词： logic gates logic functions Performance evaluation Optimization Memristors Electrodes Transistors Implication logic logic-in-memory memristor Boolean algebra RRAM

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logic Neural Networks for Efficient FPGA Implementation

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2024年

作者： Ramirez, Ivan Garcia-Espinosa, Francisco J. Concha, David Aranda, Luis Alberto Univ Rey Juan Carlos CAPO Res Grp Madrid 28933 Spain

logic Neural Networks (LNNs) represent a new paradigm for implementing neural networks in hardware devices such as Field-Programmable Gate Arrays (FPGAs). These network architectures exhibit unique attributes that can leverage the inherent parallelism of FPGAs, enabling the development of networks characterized by low power consumption and fast inference capabilities. Despite their potential advantages, the relative novelty of LNNs poses a challenge, as there are currently no established guidelines for defining their architectures. In this paper, we present a comprehensive study of LNNs, aiming to address the existing gap in understanding and guide decision-making during the design phase. Through systematic experimentation and analysis, we explore various aspects of logic networks, including their impact on inference time, power consumption, and overall simplicity. The findings derived from these experiments provide valuable insights for the creation of improved networks, thereby paving the way for further advancements in this field.

关键词： logic gates Biological neural networks Training Neurons logic Field programmable gate arrays Hardware logic functions Accuracy Network architecture Field-programmable gate array (FPGA) hardware implementation logic neural network (LNN) network architectures

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Ultra-Low Power Consumption Artificial Photoelectric Synapses Based on Lewis Acid Doped WSe2 for Neuromorphic Computing

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SMALL 2024年第51期20卷 e2406402页

作者： Ma, Mingjun Huang, Chaoning Yang, Mingyu He, Dong Pei, Yongfeng Kang, Yufan Li, Wenqing Lei, Cheng Xiao, Xiangheng Wuhan Univ Inst Technol Sci Wuhan 430072 Hubei Peoples R China Wuhan Univ Sch Phys & Technol Hubei Nucl Solid Phys Key Lab Wuhan 430072 Peoples R China

Capitalizing on the extensive spectral capacity and minimal crosstalk properties inherent in optical signals, photoelectric synapses are poised to assume a pivotal stance in the realm of neuromorphic computation. Herein, a photoelectric synapse based on Lewis acid-doped semiconducting tungsten diselenide (WSe2) is introduced, exhibiting tunable short-term and long-term plasticity. The device consumes a mere 0.1 fJ per synaptic operation, which is lower than the energy required by a single synaptic event observed in the human brain. Furthermore, these devices demonstrate high-pass filtering capabilities, highlighting their potential in image-sharpening applications. In particular, by synergistically modulating the photoconductivity and electrical gate bias, versatile logic capabilities are demonstrated within a single device, enabling it to flexibly perform both Boolean AND and OR gate operations. This work demonstrates a viable approach for Lewis acid-treated TMDs to realize multifunctional photoelectric synapses for neuromorphic computing.

关键词： 2D materials high-pass filtering logic functions optoelectronic synapses

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Importance of stochastic components for Ising Hamiltonian-based invertible logic

Importance of stochastic components for Ising Hamiltonian-ba...

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IEEE Silicon Nanoelectronics Workshop (SNW)

作者： Hutin, L. Talatchian, P. Vaz, P. Ilha El Valli, A. Sidi Bazzi, A. Phan, N. -T. Andrieu, F. CEA Leti Minatec Grenoble France Univ Grenoble Alpes SPINTEC CEA CNRS Grenoble France

ISBN: (数字)9781665459792

ISBN: (纸本)9781665459792

This work is a case study of synthesizing networks of binary stochastic units to perform Boolean logic functions and their inverse based on the intrinsic minimization of a Hamiltonian energy function. In particular, we shed light and provide some intuition on the role of stochasticity and the ability to adjust the network temperature in generating correct results, at various functional complexity levels.

关键词： Conferences Minimization logic functions Silicon Complexity theory Nanoelectronics

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Buffer Reduction Via N-Phase Clocking in Adiabatic Quantum-Flux-Parametron Benchmark Circuits

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IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY 2021年第6期31卷 1-8页

作者： Saito, Ro Ayala, Christopher L. Yoshikawa, Nobuyuki Yokohama Natl Univ Grad Sch Engn Sci Yokohama Kanagawa 2408501 Japan Yokohama Natl Univ Inst Adv Sci Yokohama Kanagawa 2408501 Japan Yokohama Natl Univ Dept Elect & Comp Engn Yokohama Kanagawa 2408501 Japan

Adiabatic quantum-flux-parametron (AQFP) logic is a superconductor logic family capable of producing extremely low-energy computing systems. However, AQFP circuitry has some challenges to overcome before it can go into practical use, and improving circuit integration is one of them. Conventionally, a four-phase clocking distribution has been utilized as the power-clock network for AQFP circuits. This method requires gates to transmit data signal currents on adjacent phases. The drawback to four-phase clocking is not only the large latency due to limiting signal propagation to four-stages of logic in a single cycle, but also the enormous amount of signal buffering that is required for large circuits. Buffering uses up valuable area on the chip. We propose the adoption of an n-phase clocking method to not only reduce the latency of AQFP circuits but to also reduce the number of buffers for n larger than 4. When the number of phases per clock cycle increases by x times, we show that the number of buffers can be decreased to 1/x times in a number of AQFP benchmark circuits.

关键词： logic gates Clocks Timing Superconducting logic circuits Superconducting integrated circuits Adiabatic logic functions multi phase clocking retiming AQFP logic superconductor electronics logic synthesis

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