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IEEE International Symposium on Circuits and Systems

作者： Ching-Wen Lin Chung-Ho Chen Institute of Computer and Communication Engineering National Cheng Kung University Tainan Taiwan R.O.C

ISBN: (纸本)9781479934331

We propose an unambiguous instruction cache software-based self-testing methodology that can generate a reliable result to precisely determine the test passed or not. We present testing cases that cause ambiguous cache testing results and propose five principles of test pattern selection to prevent these situations from occurring. To preserve the order of march sequence in testing an I-cache, we leverage cache bank and cache disable operations. In this way, we are able to implement any march algorithm without violating the sequence order. Finally, we present a case study for ARM v5 ISA processor that has an 8KB instruction cache. We use the march C- algorithm and achieve 100% of inter-word coverage and more than 97% of intra-word coverage evaluated by the RAMSES simulator.

关键词： I-cache testing SBST march algorithm ARM

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Fault Modeling and Analysis of LP Mode FinFET SRAMArrays

Fault Modeling and Analysis of LP Mode FinFET SRAMArrays

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作者： Coimbatore Raamanujan, Sudarshan University of Cincinnati

学位级别：master

The need to keep up with Moore''s law calls for highpacking density in chips. Due to this very reason, IC fabricationindustry is transforming from using conventional planar transistorsto using 3D transistors, of which FinFET proves to be most viablebecause of its good short channel characteristics and ease offabrication. Leakage power consumption has been a major concernconsidering the CMOS technology and it proves vital to reduce ***, especially in LP mode provide design flexibility bycontrolling Vth to reduce leakage by trading off delay. In thisresearch, we design an LP mode SRAM array and compare it with asimilar SG mode design for performance, power and reliability. Wethen model all possible spot defects in HSPICE. We also discuss howleakage current could drastically increase due to resistive opensat back gates. In our results, we find one new fault model and wepropose a march algorithm to detect all the fault behaviors foundin our simulations

关键词： Computer Engineering FinFET LP mode SG and LP mode comparison Fault modeling Read destructive coupling fault Unique behavior at back gate march algorithm

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Fault Modeling and Fault Type Distinguishing Test Methodsfor Digital Microfluidics Chips

Fault Modeling and Fault Type Distinguishing Test Methodsfor...

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作者： Sun, Xinyu University of Cincinnati

学位级别：master

Physical defects in digital microfludics chips (DMCs)can be very complicated and extremely difficult to find precisemodels, because each defect may occur anywhere. In this thesis, wedevelop high-level abstract fault models based on investigating thefaulty and fault-free behaviors of droplet moving. Two new faultmodels that were not found previously are proposed to enhance thereliability of DMCs. We believe that the high-level fault modelscan completely cover all defects involving two cells in a DMCarray. Based on the new high-level fault models, we propose marchalgorithms (march-d and march-p/p+) to generate test patterns thatcan detect and distinguish fault types for each faulty digitalmicrofludics chip. This is accomplished by merging both march-d andpart of march-p without causing too much test length *** algorithms are implemented into a FPGA board attached to thesimulated digital microfluidics chip such that built-in self-testcan be accomplished without human intervention. We also develop anEDA tool and simulation platform for the proposed DMC-BIST *** results demonstrate that the proposed fault models,test and fault type distinguishing methods, built-in self-testcircuit design, and emulation tool can effectively and efficientlyachieve high quality test with minimal test cost

关键词： Computer Engineering Fault modeling Test methods BIST Digital microfluidics chip Microfluidics EDA march algorithm

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Development of Automated Neighborhood Pattern Sensitive Fault Syndrome Generator for SRAM

Development of Automated Neighborhood Pattern Sensitive Faul...

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10th IEEE International Conference on Semiconductor Electronics (ICSE)

作者： Rusli, J. R. Sidek, R. M. Zuha, W. H. Wan Univ Kuala Lumpur Dept Elect British Malaysia Inst Kuala Lumpur Malaysia Univ Putra Malaysia Dept Elect & Elect Engn Serdang 43400 Malaysia

ISBN: (纸本)9781467323963;9781467323956

With the increasing complexity of memory devices, fault diagnosis is becoming as important as fault detection. Fault diagnosis is to locate and identify type of fault. One of the memory faults is Neighborhood Pattern Sensitive Faults (NPSF) which is one of the faults that are hard to test due to higher number of cells to be tested at one time. To improve the process of analyzing NPSF detection and to generate the fault syndrome for NPSF diagnosis, an Automated NPSF Syndrome Generator (ANPSFSG) is developed. A proven march algorithms are used in this generator to verify the efficiency of this generator by producing the fault coverage and diagnostic resolution. A user-friendly Graphical User Interface (GUI) of ANPSFSG is also developed by using Microsoft Visual Basic software to load the algorithm under test and display the results.

关键词： SRAM NPSF ANPSFSG GUI march algorithm memory diagnosis memory testing memory fault syndrome

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Embedded Memory Fail Analysis for Production Yield Enhancement

Embedded Memory Fail Analysis for Production Yield Enhanceme...

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22nd Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference (ASMC)

作者： Baltagi, Youssef Rosi, Daniele Li Tancorre, Vincenzo Garagnon, Christophe Faehn, Eric Barone, Mario Appello, Davide Suzor, Christophe STMicroelect ZI Rousset F-13106 Rousset France STMicroelectronics I-20041 Agrate Brianza Italy Synopsys Inc Mountain View CA 94043 USA

ISBN: (纸本)9781612844091

The traditional approach for memory fail bitmap analysis is to identify the topological signatures and perform a Failure Analysis investigation on the most frequent signatures, based on the (x,y) coordinates of the fails. This approach is inappropriate when a large portion of the fails are single bits, because too many investigations are required to statistically identify the major repetitive failure mechanisms. This becomes a problem for fast product development and production yield ramp. This paper presents a methodology to classify single fail bits by their unique fault signature, based on the sequence of failing march element read operations from multiple data backgrounds, in a standard Memory BIST flow. These classifications allow investigations to focus on the most important failure mechanisms with greatest yield impact. The methodology is demonstrated in an industrial environment, with identification of critical yield detractors. Starting from a yield problem associated to MBIST failures at high operating temperature, the fault signatures were used to identify a static noise margin parametric problem and a dislocation fault physical problem.

关键词： Bitmap MBIST Yield march algorithm Fault Signature

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Optimized BIST for Embedded Dual-Port RAMs

Optimized BIST for Embedded Dual-Port RAMs

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53rd Midwest Symposium on Circuits and Systems (MWSCAS 2010)

作者： Karunaratne, Maddu Oomman, Bejoy Univ Pittsburgh Pittsburgh PA 15260 USA Genesys Testware Inc Fremont CA 94539 USA

ISBN: (纸本)9781424477739

This paper describes new optimal test pattern generation algorithms for embedded dual-port random access memories (DPRAMs) which have two independent read-write ports. They are widely used in networking and communications integrated circuits (IC). The widely available standard extensions of march algorithms for DPRAMs are not guaranteed to detect certain inter-port coupling faults which are explained in here. This paper describes a novel optimal test method using march test algorithms that also cover such faults efficiently.

关键词： BIST Dual-port Fault model march algorithm

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The data and read/write controller for march-based SRAM diagnostic algorithm MBIST

The data and read/write controller for March-based SRAM diag...

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IEEE Student Conference on Research and Development

作者： Masnita, M., I Zuha, Wan W. H. Sidek, R. M. Halin, I. A. Univ Putra Malaysia Dept Elect Engn Serdang 43400 Malaysia

ISBN: (纸本)9781424451876

This paper presents the implementation of march-based algorithm as proposed [1] into an Memory Built-In Self-Test (MBIST) data and read/write controller. The design uses the approach of Finite State Machine (FSM)-based architecture which is more plausible since the design was the part of the engine that will be exclusively developed for the testing of this algorithm alone. This controller will represent a portion of MBIST engine that can be incorporated together with other portions to build a complete MBIST engine.

关键词： functional fault models (FFMs) march algorithm stuck-at faults (SAF) memory built in self test (MBIST) finite state machine (FSM)

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12N Test Procedure for NPSF Testing and Diagnosis for SRAMs

12N Test Procedure for NPSF Testing and Diagnosis for SRAMs

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IEEE International Conference on Semiconductor Electronics

作者： Julie, R. R. Wan, Zuha W. H. Sidek, R. M. Univ Putra Malaysia Dept Elect & Elect Engn Serdang Malaysia

ISBN: (纸本)9781424425600

Testing and diagnosis techniques play a key role in the advance of semiconductor memory technologies. The challenge of failure detection has attracted investigation on efficient testing and diagnosis algorithm for better fault coverage and diagnostic resolution. march algorithms are widely used in SRAM testing to detect and diagnose SRAM fault model since they are relatively simple and yet providing high fault coverage and diagnostic resolution. In this case to achieve high fault coverage the structure of the consecutive memory backgrounds are very important. This paper aims to prove the efficiency of march 12N algorithm in term of detection and identification capability and locate the NPSF model fault. The details of test and diagnosis procedures for NPSF are demonstrated in this paper. The fault detection and diagnostic of the SRAM memories in this paper is verified and proven. The required march elements, detection requirement, detection conditions and fault syndromes are also enlightened. Furthermore, these particulars are required to determine a good algorithm other applications.

关键词： Neighborhood Pattern Sensitive Fault Test Procedure march algorithm multi data background SRAM

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Fault modeling and detection for drowsy SRAM caches

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2007年第6期26卷 1084-1100页

作者： Pei, Wei Jone, Wen-Ben Hu, Yiming Sun Microsyst Inc Sunnyvale CA 94086 USA Univ Cincinnati Dept Elect & Comp Engn & Comp Sci Cincinnati OH 45221 USA

Due to the spatial-locality property of data caches and the temporal-locality property of instruction caches, significant leakage reduction can be achieved by switching a large number of cache lines into the low-power standby or drowsy mode. It has been shown that 80%-90% of the data cache lines can be maintained in drowsy state without affecting the performance by more than 0.6% (IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 2, pp. 167-184, Feb. 2004). However, with the introduction of the drowsy-cache design technique, new fault behaviors appear and more restrictive design rules must be applied to the chip fabrication process. In this paper, we simulate all possible spot defects (SDs) under normal mode and drowsy mode in different resistance regions using HSpice. Six new fault models appear. with the introduction of drowsy mode for memory arrays. When we derive a march algorithm for the new fault models of this low-power cache, several simplification rules are utilized to reduce the test complexity. According to these simplification rules, each of these new faults has its equivalent counterpart existent in both data caches and instruction caches. As a result, we develop a march algorithm which can detect all SDs in either data caches or instruction caches. Since some faults occur only in drowsy mode, a built-in self-repair (BISR) scheme is developed. By utilizing BISR, the cache can still work even if some cache lines fail to work in drowsy mode.

关键词： built-in self-repair drowsy cache fault modeling low-power design march algorithm memory testing

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Fault detection and diagnosis for multi-level cell flash memories

Fault detection and diagnosis for multi-level cell flash mem...

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23rd IEEE Instrumentation and Measurement Technology Conference

作者： Martin, Robert R. Jone, Wen-Ben Das, Sunil Intel Corp Flash Prod Grp 1900 Prairie City Rd Folsom CA 95630 USA Univ Ottawa Sch Informat Technol & Engn Ottawa ON K1N 6N5 Canada

ISBN: (纸本)9780780393592

Single bit per cell (SBC) flash memories have been widely used and many efficient testing and diagnosis methodologies have been proposed. On the other hand, their multi level cell counterparts are relatively not well-known, even though they have many advantages such as low area, high density, low power and short access time. To the best of our knowledge, no research papers have been published for multi level cell (MLC) flash memory testing and diagnosis. This paper is an attempt to bridge this gap by providing a simple solution to test and diagnose an MLC flash memory array. The fault model proposed takes into account many physical defects which cause the state of a memory cell to change. The universal test algorithm and the flash diagnosis (FDA) march algorithm proposed in this paper are a first of its kind for MLC flash. Their full fault coverage for the fault model we Propose in this work, low complexity and test time make them an attractive methodology for testing and diagnosing faults for multi level flash memories.

关键词： multi level cell flash memory march algorithm fault diagnosis fault testing

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