检索结果-内蒙古大学图书馆

11th Asia and South Pacific Design Automation Conference

作者： Hwang, Chanseok Pedram, Massoud Univ Southern Calif Dept Elect Engn Syst Los Angeles CA 90089 USA

ISBN: (纸本)0780394518

In this paper, we present a new timing-driven placement algorithm, which attempts to minimize zigzags and crisscrosses on the timing-critical paths of a circuit. We observed that most of the paths that cause timing problems in the circuit meander outside the minimum bounding box of the start and end nodes of the path. To limit this undesirable behavior, we impose a physical constraint on the placement problem, i.e., we assign a preferred signal direction to each critical path in the circuit. Starting from an initial placement solution, by using a move-based optimization strategy, these preferred directions force cells to move in a direction that maximizes the monotonic behavior of the timing-critical paths in the new placement solution. To make the direction assignment tractable, we implicitly group all circuit paths into a set of input-output conduits and assign a unique preferred direction to each such conduit. We integrated this idea into a recursive bipartitioning-based placement framework with a min-cut objective function. Experimental results on a set of standard placement benchmarks show that this approach improves the result of a state-of-the-art industrial placement tool for all the benchmark circuits while increasing the wire length by a tolerable amount.

关键词： circuit CAD integrated circuit design timing benchmark circuits circuit timing-critical paths industrial placement tool input-output conduits min-cut objective function monotone cell ordering constraints move-based optimization strategy recursive biparti circuit CAD integrated circuit design placement Wire length Paths ZIGZAG Byways placement algorithm

来源：评论

学校读者我要写书评

暂无评论

Failure-Aware Application placement Modeling and Optimization in High Turnover DevOps Environment 12

Failure-Aware Application Placement Modeling and Optimizatio...

引用

12th IEEE International Conference on Cloud Computing (IEEE CLOUD) held as Part of IEEE World Congress on Services (IEEE SERVICES)

作者： Suk, Tonghoon Hwang, Jinho Bulut, Muhammed Fatih Zeng, Zemei IBM TJ Watson Res Ctr New York NY 10598 USA Univ Calif Berkeley Berkeley CA 94720 USA

ISBN: (纸本)9781728127057

DevOps (software DEVelopment and information technology OPerationS) has established a culture and environment, in which building, testing, and releasing software happen more rapidly, frequently, and reliably through automated pipelines. To support this high turnover application cycle, the cluster orchestration frameworks such as Kubernetes or Docker Swarm have evolved to provide high flexibility and reliability. However, while cluster orchestrators run on the cloud infrastructure, any failure incurred from the infrastructure can directly impact the nodes of a cluster, so infrastructure failures can disrupt applications running on the cluster. In this paper, we propose proactive application placement algorithms with prediction of infrastructure failures. The proposed algorithms utilize failure-risk measurements, Failure-Index, determined from turnover rate of applications and prediction of infrastructure failures. We build stochastic models for application turnover and infrastructure failure processes, and provide various types of Failure-Index. Our placement algorithms are implemented in an orchestration framework, Kubernetes, and in the simulation model. Experimental results show that our methods reduce the amount of application disruption by 20% than the state-of-the-art algorithms in Kubernetes.

关键词： DevOps Microservices placement algorithm

来源：评论

学校读者我要写书评

暂无评论

VNF-AAP: Accelerator-aware Virtual Network Function placement

VNF-AAP: Accelerator-aware Virtual Network Function Placemen...

引用

IEEE Conference on Network Function Virtualization and Software Defined Networks (NFV-SDN)

作者： Sharma, Gourav Prateek Tavernier, Wouter Colle, Didier Pickavet, Mario Univ Ghent IMEC Dept Informat Technol IDLab Ghent Belgium

ISBN: (纸本)9781728145457

Network Function Virtualization aims to migrate packet-processing tasks from special-purpose appliances to Virtual Network Functions (VNFs) running on x86 or ARM servers. However, achieving the line-rate packet-processing for VNFs running on CPUs can be a challenging task. External hardware accelerators can be used to offload heavy-lifting tasks (e.g. en/decryption and hashing) from performance-critical VNFs. State-of-the-art VNF placement algorithms only consider compute resources while assigning VNFs on server nodes. We propose a placement algorithm which takes into consideration hardware accelerator resources in addition to compute resources. For evaluation, we compare the performance of our approach with the Integer Linear Program (ILP) method and also with the state-of-the-art best-fit method of VNF placement.

关键词： NFV hardware accelerator FPGA placement algorithm allocation

来源：评论

学校读者我要写书评

暂无评论

Temporal placement for run-time reconfiguration

Temporal placement for run-time reconfiguration

引用

19th IEEE Canadian Conference on Electrical and Computer Engineering

作者： Nahas, Carlos Guevara, Ricardo Villalobos Groza, Voicu Univ Ottawa Sch Informat Technol & Engn Ottawa ON K1N 6N5 Canada

ISBN: (纸本)9781424400379

In this paper, we propose the use of an algorithm that will improve the performance of the FPGA placement task for Run-Time Reconfiguration (RTR) computing. Previous literature will be referenced for the sake of presenting related work, as well as to present some algorithms that can be used for the placement of static, compile-time reconfigurable devices. These algorithms will then be examined in order to propose a placement algorithm that will be used in further RTR research.

关键词： run-time reconfiguration placement algorithm

来源：评论

学校读者我要写书评

暂无评论

The Road Less Traveled: Congestion-Aware NoC placement and Packet Routing for FPGAs 34

The Road Less Traveled: Congestion-Aware NoC Placement and P...

引用

34th International Conference on Field-Programmable Logic and Applications (FPL)

作者： Shahrouz, Soheil Gholami Betz, Vaughn Univ Toronto Dept Elect & Comp Engn Toronto ON Canada

ISBN: (纸本)9798331530082;9798331530075

To help scale to ever-larger and more complex designs, recent FPGA architectures now integrate network-on-chips (NoCs). NoCs help transfer high-bandwidth data over long distances within the chip without using scarce low-delay long routing wire segments. While NoC-enhanced FPGAs aid system integration and design reuse, they also complicate FPGA computer-aided design (CAD) flows by introducing new constraints and metrics. placement and routing needs to optimize NoC metrics like latency and bandwidth utilization and avoid link oversubscription (congestion), while simultaneously optimizing the programmable routing resource usage of the design modules attached to NoC routers. In this work we develop several new approaches to reduce NoC congestion while minimizing the impact on other design metrics. First, we incorporate a NoC link congestion cost into the placement engine of the open-source CAD flow, versatile place & route (VPR). Second, we integrate turn model NoC routing algorithms into the placement engine to leverage path diversity to further reduce congestion. On average over a suite of 29 benchmarks combining placement congestion modeling with turn model packet routing reduces NoC congestion by 90.7% at the cost of increasing aggregate bandwidth demand by 4%. In cases where the enhanced placement engine and NoC routing fail to fully resolve congestion, we formulate NoC routing as a boolean satisfiability (SAT) problem. This approach yields significant additional improvements;the combined algorithm reduces congestion by 95.1% compared to the baseline placement. Finally, we enhance the reinforcement learning (RL) agent in VPR's placement engine by introducing a NoC-aware move type, resulting in an 8.8% reduction in wirelength on designs that make extensive use of the NoC.

关键词： FPGA network-on-chip computer-aided design placement algorithm

来源：评论

学校读者我要写书评

暂无评论

Testability-driven layout of combinational circuits

引用

VLSI DESIGN 1998年第4期7卷 347-352页

作者： Ravikumar, CP Sharma, N Indian Inst Technol Dept Elect Engn New Delhi 110016 India

The layout of a circuit can influence the probability of occurrence of faults. In this paper, we develop algorithms that can take advantage of this fact to reduce the chances of hard-to-detect (HTD) faults from occurring. We primarily focus on line bridge faults in this paper. We define a bridge fault f as an HTD fault if an automatic test pattern generator fails to generate a test vector for f in a reasonable amount of CPU-time. It is common practice to drop such HTD faults from consideration during test generation. The chip fault coverage achieved by a test set is poor if the fault set consists of many HTD faults. We can combat this problem by avoiding altogether, or by reducing the probability of, the occurrence of HTD faults. In this paper, we consider hard-to-detect bridging faults and show how module placement rules can be derived to reduce the probability of these faults. A genetic placement algorithm that optimizes area while respecting these rules is presented. The placement algorithm has been implemented for standard-cell layout style on a SUN/SPARC and tested against several sample circuits.

关键词： bridge faults placement algorithm genetic algorithm

来源：评论

学校读者我要写书评

暂无评论

RECOVERY POINT SELECTION ON A REVERSE BINARY-TREE TASK MODEL

引用

IEEE TRANSACTIONS ON SOFTWARE ENGINEERING 1989年第8期15卷 963-976页

作者： CHEN, SK TSAI, WT THURAISINGHAM, MB UNIV MINNESOTA DEPT COMP SCIMINNEAPOLISMN 55455 MITRE CORP BEDFORDMA 01730

In this paper we analyze the complexity of placing recovery points where the computation is modeled as a reverse binary tree task model. The objective is to minimize the expected computation time of a program in the presence of faults. The method can be extended to an arbitrary reverse tree model. For uniprocessor systems, we propose an optimal placement algorithm. For multiprocessor systems, we describe a procedure to compute its performance. Since no closed form solution is available, we propose an alternative measurement which has a closed form formula. Based upon this formula, we devise algorithms to solve the recovery point placement problem. The estimated formula can be extended to include communication delays where the algorithm devised still applies. [ABSTRACT FROM AUTHOR]

关键词： AIgorithms placement algorithm recovery block.

来源：评论

学校读者我要写书评

暂无评论

Incremental design methodology for multimillion-gate FPGAs

引用

JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 2005年第5期14卷 1015-1026页

作者： Ma, J Athanas, P Huang, X Univ New Orleans Dept Elect Engn New Orleans LA 70148 USA Virginia Tech Dept Elect & Comp Engn Blacksburg VA 24060 USA

This paper presents an FPGA design methodology that can be used to shorten the FPGA design-and-debug cycle, especially as the gate counts increase to multimillions. Core-based incremental placement algorithms, in conjunction with fast interactive routing, axe investigated to reduce the design processing time by distinguishing the changes between design iterations and reprocessing only the changed blocks without affecting the remaining part of the design. When combined with a background refinement thread, the incremental approach offers the instant gratification that designers expect, while preserving the fidelity attained through batch-oriented programs. An integrated FPGA design environment is then developed based on the incremental placer and its background refiner. The results show that the incremental design methodology is in orders of magnitude faster than the competing approaches such as the Xilinx M3 tools without sacrificing too much quality.

关键词： incremental techniques placement algorithm JBits APIs design tool core PPGA

来源：评论

学校读者我要写书评

暂无评论

Latency-aware virtual desktops optimization in distributed clouds

引用

MULTIMEDIA SYSTEMS 2018年第1期24卷 73-94页

作者： Guo, Tian Shenoy, Prashant Ramakrishnan, K. K. Gopalakrishnan, Vijay Worcester Polytech Inst Worcester MA 01609 USA Umass Amherst Amherst MA USA UC Riverside Riverside CA USA AT&T Labs Bedminster NJ USA

Distributed clouds offer a choice of data center locations for providers to host their applications. In this paper, we consider distributed clouds that host virtual desktops which are then accessed by users through remote desktop protocols. Virtual desktops have different levels of latency-sensitivity, primarily determined by the actual applications running and affected by the end users' locations. In the scenario of mobile users, even switching between 3G and WiFi networks affects the latency-sensitivity. We design VMShadow, a system to automatically optimize the location and performance of latency-sensitive VMs in the cloud. VMShadow performs black-box fingerprinting of a VM's network traffic to infer the latency-sensitivity and employs both ILP and greedy heuristic based algorithms to move highly latency-sensitive VMs to cloud sites that are closer to their end users. VMShadow employs a WAN-based live migration and a new network connection migration protocol to ensure that the VM migration and subsequent changes to the VM's network address are transparent to end-users. We implement a prototype of VMShadow in a nested hypervisor and demonstrate its effectiveness for optimizing the performance of VM-based desktops in the cloud. Our experiments on a private as well as the public EC2 cloud show that VMShadow is able to discriminate between latency-sensitive and insensitive desktop VMs and judiciously moves only those that will benefit the most from the migration. For desktop VMs with video activity, VMShadow improves VNC's refresh rate by 90% by migrating virtual desktop to the closer location. Transcontinental remote desktop migrations only take about 4 min and our connection migration proxy imposes 13 mu s overhead per packet.

关键词： Distributed clouds Virtual desktop placement algorithm

来源：评论

学校读者我要写书评

暂无评论

Implementing fine grain processor arrays on field-programmable logic

引用

INTEGRATED COMPUTER-AIDED ENGINEERING 2000年第1期7卷 53-66页

作者： Vassányi, I Univ Veszprem Dept Informat Syst H-8200 Veszprem Hungary

The structure of Field programmable Gate Arrays (FPGAs) naturally fits that of fine grain array algorithms. The paper investigates the geometrical and layout-related implementation problems of FPGA-based processor arrays. A general methodology for implementing parametrized array processors on FPGAs is presented. Then, a detailed layout algorithm is proposed. A new feature of the algorithm is the uniform treatment of inter- and intra-module nets that allows the layout of the basic processor to be optimized with respect to the critical path of the whole, arbitrarily large processor array. The approach is demonstrated on a massively parallel processor array for binary morphology.

关键词： ARRAY PROCESSORS PROCESSOR massively parallel processors Formal logic Field programmable gate arrays placement algorithm microparticles algorithms layouts

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：