In this paper, a smart image sensor for real-time and high-resolution three-dimensional (3-D) measurement to be used for sheet light projection is presented. It realizes not only a sufficiently high frame rate for rea...
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In this paper, a smart image sensor for real-time and high-resolution three-dimensional (3-D) measurement to be used for sheet light projection is presented. It realizes not only a sufficiently high frame rate for real-time 3-D measurement, but also high pixel resolution due to a small pixel circuit and high subpixel accuracy due to gravity center calculation using an intensity profile. Simulation results show that the ultimate frame rate is 32.6 k frames/s (i.e., 31.8 range_map/s) in a 1024 x 1024 pixel sensor. A 3-b intensity profile allows subpixel accuracy under 0.1 pixel. The sensor using this architecture can acquire a two-dimensional (2-D) image as well, so a texture-mapped 3-D image can be reproduced by the same sensor. A 128 x 128 smart image sensor has been developed and successfully tested. A 2-D image, a range map, and a texture-mapped 3-D image have been acquired by the 3-D measurement system using the fabricated sensor.
Lookahead signals to form the multilevel folding architecture for priority-encoding-based designs was used to improve the performance to the order of O (log N). Analysis showed that both the multilevel lookahead and t...
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Lookahead signals to form the multilevel folding architecture for priority-encoding-based designs was used to improve the performance to the order of O (log N). Analysis showed that both the multilevel lookahead and the multilevel folding techniques could be easily merged and implemented in the dynamic CMOS circuits. For the 256-bit priority encoder, the new design adopting all the proposed techniques can achieve nearly ten times performance while spending nearly half the power consumption as compared to the conventional design, utilizing only a simple lookahead structure. For the 64-bit incrementer/decrementer, the new design adopting all the proposed techniques requires less than one-third delay time as compared to a high-speed carry-select adder (CSA)-based incrementer/decrementer. The power consumption evaluated at the maximum operating frequency and the transistor count of the new incrementer/decrementer are also reduced to 67% and 35%, respectively, as compared to the CSA-based design. The measurement results indicate that the proposed 256-bit priority encoder and the proposed 64-bit incrementer/decrementer can operate up to 116 and 139 MHz, respectively, when they are designed based on a 0.6-mum CMOS technology.
The design of two high-performance priority encoders is presented. The key techniques for high speed are twofold. First, a multilevel look-ahead structure is developed to shorten the critical path effectively Second, ...
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The design of two high-performance priority encoders is presented. The key techniques for high speed are twofold. First, a multilevel look-ahead structure is developed to shorten the critical path effectively Second, this look-ahead structure is realized efficiently by the NP Domino CMOS logic, and all the dynamic gates have a parallel-connected circuit structure. For high speed and low power at the same time, the series-connected circuit structure is adopted in the less critical paths to reduce the switching activity, but such a design needs to cascade two n-type dynamic gates directly resulting in the race problem. A special circuit technique is utilized to rescue this problem. Several 32-bit priority encoders are designed to evaluate the feasibility of the proposed techniques. The best new design realizes a three-level look-ahead structure, and it achieves 65% speed improvement, 20% layout area reduction, and 30% power reduction simultaneously as compared to the conventional design [1] with a simple look-ahead structure.
LZ77 code obtains high compression ratios by searching for and eliminating repeated data. The parallel search capability of content addressable memory (CAM) allows very high-speed hardware implementation. This article...
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LZ77 code obtains high compression ratios by searching for and eliminating repeated data. The parallel search capability of content addressable memory (CAM) allows very high-speed hardware implementation. This article describes smaller and faster CAM and improvements of a priority encoder to get a higher compression ratio. By modifying the critical path, which is the feedback to the search logic, circuit size can be reduced and speed can be doubled. A conventional priority encoder outputs an absolute address according to the search result. The encoders shown here output the relative address, or output the difference in length between the longest and the second-longest matching data. Compression formats that cannot be handled by the conventional encoder, and a coding scheme for higher compression ratio, can be adopted by using the new encoders. (C) 1999 Scripta Technica.
This paper describes a 288-kb (8K words x 36 b) fully parallel content addressable memory (CAM) LSI using a compact dynamic CAM cell with a stacked-capacitor structure and a novel hierarchical priority encoder. The st...
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This paper describes a 288-kb (8K words x 36 b) fully parallel content addressable memory (CAM) LSI using a compact dynamic CAM cell with a stacked-capacitor structure and a novel hierarchical priority encoder. The stacked-capacitor structure results in a very compact dynamic CAM cell (66 mum2) which is operationally stable. The novel hierarchical priority encoder reduces the circuit area and power dissipation. In addition, a new priority decision circuit is introduced. The chip size is 10.3 x 12.0 mm2 using a 0.8-mum CMOS process technology. A typical search cycle time of 150 ns and a maximum power dissipation of 1.1 W have been obtained using circuit simulation. In fabricated CAM chips, we have verified the performance of a search operation at a 170-ns cycle and have achieved a typical read/write cycle time of 120 ns. This CAM LSI performs large-scale search operations very efficiently, and therefore, has the possibility of broad applications to high-performance artificial intelligence machines and data-base systems.
A rule for the selection of the learning coefficient, eta, for use in back propagation with batch training of neural networks is presented. The length of the error gradient is shown to increase as more training set ex...
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A rule for the selection of the learning coefficient, eta, for use in back propagation with batch training of neural networks is presented. The length of the error gradient is shown to increase as more training set examples are presented. This results in slow training or nonconvergence if eta is not decreased as the number of input examples increases. The effect of a momentum term is shown to allow a range of eta's to produce similar training rates. Two networks having identical topology are trained at different tasks, one with few training patterns (16) and one with many (192). Distinctly different values of eta are shown to produce good training for the two networks. We propose selecting eta-equal to 1.5 divided by the square root of the sum of the squares of the number of each input pattern type. Any group of similar inputs that map to identical outputs constitutes a pattern type. This rule produces a fixed value of eta that yields rapid training when coupled with a momentum coefficient of 0.9 for a wide variety of networks.
A special-purpose analog to digital (A/D) circuit using medium-scale integration ICs on a printed circuit board is developed. The circuit determines which of the eight input analog signals is the lowest and provides a...
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A special-purpose analog to digital (A/D) circuit using medium-scale integration ICs on a printed circuit board is developed. The circuit determines which of the eight input analog signals is the lowest and provides an 8-b magnitude and 3-b address output of this minimum input signal at a 0.5-MHz conversion rate. The circuit utilizes a successive approximation register, adder registers, CMOS D/A (digital/analog), parallel comparators, and a priority encoder connected in closed loop. Control is accomplished using simple flip-flop logic. Several important signal-processing applications are mentioned for this circuit as a feedback component in optical and electronic systems, utilizing associative self-organizing memory.>
Area and computation time are considered to be important measures with which VLSI circuits are evaluated. In this paper, the area-time complexity for nontrivial n-input m-output Boolean functions, such as a decoder an...
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Area and computation time are considered to be important measures with which VLSI circuits are evaluated. In this paper, the area-time complexity for nontrivial n-input m-output Boolean functions, such as a decoder and an encoder, is studied with a model similar to Brent-Kung"s model. A lower bound on area-time-product (ATαaα.≥1) for these functions is shown: for example, ATα= ω(2n. nα-l) for an n-input 2V-output decoder, and ATα= ω( n . logα-1n) for an n-input ⌈log n⌉-output encoder. The results shown in this paper are complementary to those by Brent-Kung or Thompson, and are useful for a class of functions of rather simple structures, e.g., a priority encoder, a comparator, and symmetric functions.
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