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A VME/VMX - CAMAC INTERFACE AND CRATE CONTROLLER

IEEE TRANSACTIONS ON NUCLEAR SCIENCE 1987年第4期34卷 751-755页

作者： MCPARLAND, C BIESER, F Lawrence Berkeley National Laboratory Berkeley CA USA

A VME/VMX bus interface has been designed and built to interface a VME-based data acquisition system to CAMAC. The interface communicates via a differential bus with a companion unit that functions as a CAMAC crate controller. The interface maps both VMiE and VMX address cycles into appropriate CAMAC cycles. Special diagnostic features have been incorporated in the design to allow quick fault detection and location.

关键词： CAMAC programmable logic arrays Data acquisition Instruments Laboratories Fault detection Aging Throughput Buffer storage Memory

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Initial Satellite Access Authentication Based on Doppler Frequency Shift

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IEEE WIRELESS COMMUNICATIONS LETTERS 2021年第3期10卷 498-502页

作者： Fu, Qing-Yi Feng, Yue-Hua Wang, Hui-Ming Liu, Peng Xi An Jiao Tong Univ Sch Informat & Commun Engn Xian 710049 Peoples R China Xi An Jiao Tong Univ Key Lab Intelligent Networks & Network Secur Minist Educ Xian 710049 Peoples R China Huawei Technol Wireless Technol Lab 2012 Labs Shenzhen 518000 Peoples R China

The future mobile system shall be able to support satellite access to provide an ubiquitous wireless connection service. Satellite communication is vulnerable to spoofing attacks due to the open nature of wireless channels, especially for the downlink satellite system information signalling (SIS) which has not been authenticated yet before initial access. SIS spoofing attacks would cause interferences as well as access failures or even denial of services (DoS) to the legitimate users. Thanks to the knowledge of satellite ephemeris as well as the global navigation satellite system (GNSS), Doppler frequency shift as an available physical attribute can be exploited to identify the source of SIS before the random access procedure. A physical layer authentication (PLA) approach based on Doppler frequency shift is proposed to determine whether the received SIS is from the legitimate communication satellite. Simulations show that the performance of the proposed method outperforms the channel state information (CSI) based PLA scheme.

关键词： Satellite broadcasting Authentication Doppler shift programmable logic arrays Global navigation satellite system Correlation Fading channels Physical layer authentication doppler frequency shift satellite communication

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The Peculiarities of Electret Effect in Corona Electrets Based on Nonpolar and Polar Polymers With Dispersed Montmorillonite

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IEEE TRANSACTIONS ON DIELECTRICS AND ELECTRICAL INSULATION 2022年第3期29卷 840-844页

作者： Gulyakova, Anna A. Galikhanov, Mansur F. Ma, Xingchen Zhang, Xiaoqing Fang, Peng Herzen State Pedag Univ Dept Gen & Expt Phys St Petersburg 191186 Russia Kazan Natl Res Technol Univ Dept Proc Technol Polymers & Composite Mat Kazan 420015 Russia Tongji Univ Sch Phys Sci & Engn Shanghai Key Lab Special Artificial Microstruct M Shanghai 200092 Peoples R China Chinese Acad Sci Shenzhen Inst Adv Technol CAS Key Lab Human Machine Intelligence Synergy Sy Shenzhen 518055 Peoples R China

Polyethylene (PE) and polylactide (PLA) films with 2 and 4 vol% of montmorillonite (MM) are compared to each other and to nonfilled samples. The electret characteristics of initial and composite films (values of the surface potential, effective surface charge density, and electric field strengths) are determined. Filling PE and PLA with MM improves electret properties due to changes in heterogeneous structure.

关键词： Electrets programmable logic arrays Plastics Electric potential Surface treatment Films Corona Composite films electrets polylactide (PLA) polyethylene (PE)

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A GALLIUM-ARSENIDE SDFL GATE ARRAY WITH ON-CHIP RAM

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1984年第1期19卷 10-22页

作者： VU, TT ROBERTS, PCT NELSON, RD LEE, GM HANZAL, BR LEE, KW ZAFAR, N LAMB, DR HELIX, MJ JAMISON, SA HANKA, SA BROWN, JC SHUR, MS HONEYWELL INC CTR SYST & RESMICROELECTR SECTINFRARED SENSORS GRPMINNEAPOLISMN 55413 HONEYWELL INC CTR CORP TECHNOLGAAS DIGITAL ELECTR GRPBLOOMINGTONMN 55420 UNIV MINNESOTA DEPT ELECT ENGNMINNEAPOLISMN 55455

Describes a GaAs gate array with on-chip RAM based on the Schottky diode field-effect transistor logic (SDFL) technology. The array features 432 programmable SDFL cells, 32 programmable interface input-output (I/O) buffers, and four 4/spl times/4 bit static random access memories (RAM) on a 147 mil/spl times/185 mil chip. Each SDFL cell can be programmed as a NOR gate with as many as 8 inputs with a buffered or unbuffered output or as a dual OR-NAND gate with four inputs per side. The interface I/O buffer can be programmed for ECL, TTL, CMOS, and SDFL logic families. Each 4/spl times/4 bit RAM is fully decoded using SDFL circuits (depletion-mode MESFET). Preliminary results demonstrate the feasibility of GaAs SDFL for fast gate array and memory applications.

关键词： Gallium arsenide Read-write memory logic arrays programmable logic arrays Schottky diodes FETs SRAM chips CMOS logic circuits Decoding MESFET circuits

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AN ARCHITECTURE FOR A DSP FIELD-programmable GATE ARRAY (VOL 3, PG 136, 1995)

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1995年第2期3卷 342-342页

作者： AGARWALA, M BALSARA, PT UNIV TEXAS DEPT ELECT ENGNRICHARDSONTX 75083

This paper describes an application specific architecture forfield-programmable gate arrays (FPGAs). Emphasis is placed on the logicmodule architecture and channel segmentation for the FPGAs targeted forapplication areas related to digital signal processing (DSP). Theproposed logic module architecture is well-suited for efficientimplementation of frequently used logic functions in the DSP applicationarea. This is mainly because it is possible to implement most of thesefunctions using one logic module, which results in a reduction in boththe net lengths and the number of antifuses used. The performanceimprovements are achieved by customizing the logic module architectureand the programmable interconnect to suit the requirements of DSPapplications

关键词： application specific integrated circuits digital signal processing chips field programmable gate arrays programmable logic arrays DSP field-programmable gate array antifuses application specific architecture channel segmentation logic functions logic mod ARCHITECTURE Building construction Field programmable gate arrays logic functions application specific integrated circuits programmable logic arrays digital signal processing chips

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A 24 BIT MICROPROCESSOR FOR DATA COMMUNICATION-SYSTEMS DESIGNED ON THE BASIS OF A GENERAL CELL LIBRARY

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1983年第3期18卷 250-261页

作者： MUELLERGLASER, KD CANZLER, T KLING, R SCHULTE, H Siemens AG Munich Germany

A 24-bit microprogrammed processor with 200 ns instruction cycle time has been realized as an experimental special purpose VLSI chip. The design was based on a general cell library and a set of advanced CAD tools. The technology used is a 3 /spl mu/m silicon gate, n-channel, single metallization MYMOS process. The chip integrates 9400 gate functions plus a 256/spl times/27 bit static RAM on 78.5 mm/SUP 2/.

关键词： Microprocessors Data communication Libraries Very large scale integration Costs Production Read only memory programmable logic arrays Design automation Metallization

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SOME BIOCHEMICAL EFFECTS OF GLYPHOSATE ON PLANT MERISTEMS

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JOURNAL OF EXPERIMENTAL BOTANY 1980年第125期31卷 1665-1674页

作者： COLE, DJ DODGE, AD CASELEY, JC UNIV BATH SCH BIOL SCI BATH BA2 7AY AVON ENGLAND ARC WEED RES ORG OXFORD OX5 1PF ENGLAND

Glyphosate [a nonselective, post-emergence herbicide] promoted the activity of phenylalanine ammonia lyase (PAL) in both single node rhizome buds of Agropyron repens L. Beauv. (cv. Common Couch) Headington Clone 31 and root tips of wheat seedlings, in the latter case correlating inversely with decline in respiratory activity. Differential rates of 14C-amino acid incorporation suggest that glyphosate depleted the phenylalanine protein precursor pool with resultant inhibition of protein synthesis, as evidenced by a rapid decline in the level of soluble protein. Promotion of PAL is assumed to occur by derepression through decline in end-product levels. Activities of shikimate:NADP oxidoreductase (SORase), chorismate mutase and polyphenol oxidase (PPO) were also elevated, but to lesser extents than for PAL.

关键词： SHCBP1 gene Roundup biochemistry programmable logic arrays Decline activity Meristems LRIT1 gene Polyphenol Oxidase (PPO) Derepression protein synthesis

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Adhesion dynamics of porcine esophageal fibroblasts on extracellular matrix protein-functionalized poly(lactic acid)

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BIOMEDICAL MATERIALS 2008年第1期3卷 015014 (10-015014 (10页

作者： Cai, Ning Gong, Yingxue Chian, Kerm Sin Chan, Vincent Liao, Kin Nanyang Technol Univ Sch Chem & Biomed Engn Singapore 639798 Singapore Nanyang Technol Univ Sch Mech & Aerosp Engn Singapore 639798 Singapore

Effective attachment of esophageal cells on biomaterials is one important requirement in designing engineered esophagus substitute for esophageal cancer treatment. In this study, poly(lactic acid) (PLA) was subjected to surface modification by coupling extracellular matrix (ECM) proteins on its surface to promote cell adhesion. Two typical ECM proteins, collagen type I (COL) and fibronectin (FN), were immobilized on the PLA surface with the aid of glutaraldehyde as a cross linker between aminolyzed PLA and ECM proteins. By using confocal reflectance interference contrast microscopy (C-RICM) integrating with phase contrast microscopy, the long-term adhesion dynamics of porcine esophageal fibroblasts (PEFs) on four types of surfaces (unmodified PLA, PLA-COOH, PLA-COL and PLA-FN) was investigated during 24 h of culture. It is demonstrated by C-RICM results that PEFs form strong adhesion contact on all four types of surfaces at different stages of cell seeding. Among the four surfaces, PEFs on the PLA-FN surface reach the maximum adhesion energy (9.5 x 10(-7) J m(-2)) in the shortest time (20 min) during the initial stage of cell seeding. After adhesion energy reaches the maximum value, PEFs maintain their highly deformed geometries till they reached a steady state after 20 h of culture. F-actin immunostaining results show that the evolvement of spatial organization of F-actin is tightly correlated with the formation of adhesion contact and cell spreading. Furthermore, the cell attachment ratio of PEFs on PLA in 2 h is only 26% compared with 88% on PLA-FN, 73% on PLA-COL and 36% on PLA-COOH. All the results demonstrate the effect of surface functionalization on the biophysical responses of PEFs in cell adhesion. Fibronectin-immobilized PLA demonstrates promising potential for application as an engineered esophagus substitute.

关键词： programmable logic arrays F-Actin Phase-Contrast Microscopy Spatial Organization Adsorption energy

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Benchmarking Power Generation From Multiple Wastewater Electrolytes in Microbial Fuel Cells With 3D Printed Disk-Electrodes

IEEE TRANSACTIONS ON NANOBIOSCIENCE

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IEEE TRANSACTIONS ON NANOBIOSCIENCE 2024年第3期23卷 491-498页

作者： Mao, Yuvraj Maphrio Amreen, Khairunnisa Goel, Sanket Birla Inst Technol & Sci BITS Pilani Microfluid & Nanoelect MMNE Lab MEMS Hyderabad Campus Hyderabad 500078 India Birla Inst Technol & Sci BITS Pilani Dept Elect & Elect Engn Hyderabad 500078 India St Anns Coll Women Hyderabad 500028 India

Microbial Fuel Cells (MFCs) have recently gained attention, as they are inexpensive, green in nature, and sustainable. As per the report, by Allied Market Research the global market size of MFCs will increase from $264.8 million in 2021 to $452.2 million in 2030, growing at a CAGR of 4.5%. The present work is a comparative study of various types of electrolytes that can be used in MFCs. The working electrodes were printed using conducting graphene-based Polylactic Acid (PLA) filaments with the help of a 3D printer under the principle of the fused deposition method. Simulated electrolytes and natural environmental microbial electrolytes were used here. Also, electrolytes of pure E. coli culture were studied. Lake water reported the highest power density of 8.259 mW/cm(2) while Stale E. Coli reported the lowest around 0.184 mW/cm(2). The study comprehensively lists potential wastewaters that can fuel the MFCs. With the pioneering of various comparative studies of electrolytes, one can insight into the recruitment of electrolytes with high-performance benchmarks for miniaturized energy storage and other microelectronics applications.

关键词： Electrodes Electrolytes Graphene Three-dimensional displays Wastewater programmable logic arrays Water pollution 3D printing microbial fuel cells electrolytes wastewaters power density comparative studies fused deposition modeling

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A binary link tracker for the BaBar Level 1 trigger system

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 1999年第4期46卷 928-932页

作者： Berenyi, A Chen, HK Dao, K Dow, SF Gehrig, SK Gill, MS Grace, C Jared, RC Johnson, JK Karcher, A Kasen, D Kirsten, FA Kral, JF LeClerc, CM Levi, ME von der Lippe, H Liu, TH Marks, KM Meyer, AB Minor, R Montgomery, AH Romosan, A EO Lawrence Berkeley Natl Lab Berkeley CA 94720 USA

The BABAR detector at PEP-II will operate in a high-luminosity e(+)e(-) collider environment near the Y(4S) resonance with the primary goal of studying CP violation in the B meson system. In this environment, typical physics events of interest involve multiple charged particles. These events are identified by counting these tracks in a fast first level (Level 1) trigger system, by reconstructing the tracks in "real time." For this purpose, a Binary Link Tracker Module (BLTM) was designed and fabricated for the BABAR Level 1 Drift Chamber trigger system. The BLTM is responsible for linking track segments, constructed by the Track Segment Finder Modules (TSFM), into complete tracks. A single BLTM module processes a 360 MBytes/s: stream of segment hit data, corresponding to information from the entire Drift chamber, and implements a fast and robust algorithm that tolerates high hit occupancies as well as local inefficiencies of the Drift Chamber. The algorithms and the necessary control logic of the BLTM were implemented in Field programmable Gate arrays (FPGAs), using the VHDL hardware description language. The finished 9U x 400 nun Euro-format board contains roughly 75,000 gates of programmable logic or about 10,000 lines of VHDL code synthesized into five FPGAs.

关键词： Field programmable gate arrays programmable logic arrays Detectors Resonance Mesons Physics Joining processes Robustness programmable control Hardware design languages

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