This paper proposes a simple yet effective technique for increasing the capacity and sharing the control task of any PLC through the use of multi-rate scanning. The I/O binary signals are grouped according to anticipa...
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The programmable-logic-device (PLD) code implements a pc-board-level revision-detection system that detects whether PLD pins are shorted together on a pc board. In PLD families that have no integral pin-pullup or pull...
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The programmable-logic-device (PLD) code implements a pc-board-level revision-detection system that detects whether PLD pins are shorted together on a pc board. In PLD families that have no integral pin-pullup or pulldown resistors, redefining previously unused pins as inputs means that these pins float, either causing erratic operation or indicating an improper pc-board-revision level. The software module generates a short, simple pattern, such as a square wave, onto a driver pin, REVO_OUT. An implementation of the design with the parameters set to the default values takes 16 logic cells in an Altera EP1K50BC256-3-less than 1% of the device and runs at rates as high as 185 MHz.
A list of programmablelogic device (PLD) code, Listing 1, that creates arbitrary-resolution, pulse width modulated (PWM)generators is presented. The software module given in the Listing 1 automatically generates the ...
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A list of programmablelogic device (PLD) code, Listing 1, that creates arbitrary-resolution, pulse width modulated (PWM)generators is presented. The software module given in the Listing 1 automatically generates the required hardware from two compile-time parameters, PWM_WIDTH and AVALUE. The module has two major sections, a holding register and a counter, which can be updated automatically. The design structure and flow can also be readily translated into VHDL or Verilog.
The paper presents a methodology of designing control logic that is implemented by industrial programmable logic controllers. The approach is based on discrete-event model of a plant to be controlled and a set of inte...
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The paper presents a methodology of designing control logic that is implemented by industrial programmable logic controllers. The approach is based on discrete-event model of a plant to be controlled and a set of interlock and sequential specification models. Supervisory control theory is used to test the controllability of the specifications and in the final stage, to derive a model of the admissible behaviour of the system which serves as a specification for the sequential part of the controller. A laboratory scale modular assembly line case study is presented to illustrate the practical issues of the approach.
Domotics is the technology for developing the automation of common installations in a house or building. Despite the high expectations due to the potential energy saving, comfort and security, there was a low increasi...
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Domotics is the technology for developing the automation of common installations in a house or building. Despite the high expectations due to the potential energy saving, comfort and security, there was a low increasing in the number of domotics installations. Main reasons are the diversity of existing products and the difficulties potential users perceive in their managing. Our research group has developed several software tools that simplify the design, installation and maintenance of domotics buildings. Also, they provide a friendly interface with the end user, for the local and remote supervision of the automated functions.
programmable logic controllers (PLC) are frequently used in the automation industry for the control of hybrid systems. Although the programming languages for PLCs are given in the standard IEC 61131-3, their semantics...
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programmable logic controllers (PLC) are frequently used in the automation industry for the control of hybrid systems. Although the programming languages for PLCs are given in the standard IEC 61131-3, their semantics are defined in an ambiguous and incomplete way. This holds in particular for the graphical language Sequential Function Charts (SFC), a high-level programming language comprising such interesting features as parallelism, activity manipulation, priorities and hierarchy. In this work we present a formal semantics for timed SFCs, which belong to the class of linear hybrid systems.
The new programmablelogic-devices and field programmable gate arrays (FPGA) developed by semiconductor vendors are discussed. Actel' first-generation programmable-low-impedance-circuit-element (PLICE) antifuse-te...
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The new programmablelogic-devices and field programmable gate arrays (FPGA) developed by semiconductor vendors are discussed. Actel' first-generation programmable-low-impedance-circuit-element (PLICE) antifuse-technology approach employs a metal-to-metal interconnect structure comprising polysilicon and a diffused N± region, separated by a high-impedance oxide-nitride-oxide barrier. Atmel's two FPGA architecturers, the older AT6000 and newer AT40K families, both offer dynamic partial-reprogramming capability that the company defined with reconfigurable-computing applications in mind. Triscend's A7 family brings CSOC concept to the 32-bit processor world.
Electronics miniaturization, competition, and customer demands has radically changed the micro PLC landscape. With such expanded capabilities, process control users should take a hard look at micro PLCs for small-scal...
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Electronics miniaturization, competition, and customer demands has radically changed the micro PLC landscape. With such expanded capabilities, process control users should take a hard look at micro PLCs for small-scale and distributed control applications. If a micro can do the job, a user can look forward to substantial savings. These savings are realized not only because of the low cost of the PLC, but also because of a micro's small size.
A discussion on Synapse 3220, an IP-based interconnect technology that addresses the overall complexity issues of system-on-a-chip (SoC) was presented. This interconnect technology hinges on an industry-standard socke...
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A discussion on Synapse 3220, an IP-based interconnect technology that addresses the overall complexity issues of system-on-a-chip (SoC) was presented. This interconnect technology hinges on an industry-standard socket called the Open Core Protocol (OCP). The basic concepts of OCP as a foundation technology for defining an IP core's bus interface were discussed.
The views of Colin Attenborough on the design features of 16-bit input and output USB port, are presented. This port is deviced by using a programmablelogic device and a USB interface module, which is controlled by V...
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The views of Colin Attenborough on the design features of 16-bit input and output USB port, are presented. This port is deviced by using a programmablelogic device and a USB interface module, which is controlled by Visual Basic. The FT8U245AM integrated circuit from Future Technology Devices International contains the core circuitry for a USB interface. FTDI also offers two software approaches where the device can be addressed as if it were attached to a serial port, if 'virtual com port' (VCP), drivers are used. Colin uses the dynamic-link library (DLL), which allows direct drive, to use Visual Basic in conjunction with the module. FTDI also provides royalty-free USB port drivers for Windows 98 and Windows 2000.
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