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IEEE Nuclear Science Symposium Conference 2009

作者： Huang, Wei Chiang, Shiuh-hua Wood Kleinfelder, Stuart Univ Calif Irvine Irvine CA 92697 USA

ISBN: (纸本)9781424439614

A transient waveform digitizer circuit with continuous sampling capability and real-time programmable windowed trigger generation has been fabricated and tested. Designed in 0.25 mu m CMOS, the digitizer contains a circular array of 128 sample and hold circuits for continuous sample storage, and attains 2 GHz sample speeds with up to 2 GHz analog bandwidth. Sample clock generation adopts a semi-synchronous approach, combining a phase-locked loop for highspeed clock generation and a high-speed fully-differential shift register for distributing clocks to all 128 sample circuits. Using two comparators per sample, the sample voltage levels are compared against reference levels that are set via per-comparator digital to analog converters (DACs). The 256 per-comparator 5-bit DACs compensate for offsets and allow for fine reference level adjustment. The comparator results are matched in 8-sample wide windows against up to 72 programmable patterns in real-time using a programmable logic array. Each trigger window is 8 samples-wide, overlapped sample by sample in a circular fashion through the entire 128 sample array. A trigger is flagged within 7 ns if there is a match, after which on-chip digitization can proceed via 128 parallel 10-bit converters.

关键词： Transient digitizer sample and hold analog to digital conversion programmable logic array phase-locked loop

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A 5-10 GHz SiGeBiCMOS FPGA with new configurable logic block

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MICROPROCESSORS AND MICROSYSTEMS 2005年第2-3期29卷 121-131页

作者： You, C Guo, JR Kraft, RP Chu, M Curran, P Zhou, K Goda, B McDonald, JF Rensselaer Polytech Inst Troy NY 12180 USA

This paper presents a new multiplexer based FPGA, which can operate at a clock frequency of 5-10 GHz. Redundant switches on the original signal paths are removed improving the performance. The configurable logic blocks (CLBs) power is greatly reduced by using a revised multiplexer structure and turning off unused cells dynamically. More routing capabilities are provided with more inputs/outputs in each direction than similar designs. A chip consisting of four FPGA ring oscillators was fabricated. The Spice simulation results and chip measurement, are presented, (C) 2004 Elsevier B.V. All rights reserved.

关键词： field programmable gate array gate-array high-performance low-power-design SiGe programmable logic array reconfigurable-system current mode logic

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PITIA: An FPGA for throughput-intensive applications

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2003年第3期11卷 354-363页

作者： Singh, A Mukherjee, A Macchiarulo, L Marek-Sadowska, M Univ Calif Santa Barbara Dept Elect & Comp Engn Santa Barbara CA 93106 USA Politecn Torino Dept Elect I-10129 Turin Italy

In this paper, we present a novel, high throughput field-programmable gate array (FPGA) architecture, PITIA, which combines the high-performance of application specific integrated circuits (ASICs) and the flexibility afforded by the reconfigurability of FPGAs. The new architecture, which targets datapath circuits, uses the concepts of wave steering and pipelined interconnects. We discuss the FPGA architecture and show results for performance, power consumption, clock network performance, and routability. Results for some commonly used datapath designs are encouraging with throughputs in the neighborhood of 625 MHz in 0.25-mum 2.5-V CMOS technology. Results for random benchmark circuits are also shown. We characterize designs according to their Rent's exponents and argue that designs with predominantly local interconnects are the best fit in PITIA. We also show that as technology scales down toward deep submicron, PITIA shows an increasing throughput performance.

关键词： arithmetic clustering high performance programmable logic array reconfigurable components

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A modular low dead-time coincidence system for high-resolution PET cameras

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2003年第5期50卷 1386-1391页

作者： Wang, Y Li, HD Liu, YQ Xing, T Uribe, J Baghaei, H Farrell, R Wong, WH Univ Texas MD Anderson Canc Ctr Houston TX 77030 USA

A high-resolution oncologic transformable positron emission tomography (HOTPET) is currently under development. The detector ring of the camera consists of 12 detector modules. Because the high-yield-pile-up-event-recovery (HYPER) front-end electronics are applied in this new-generation PET camera, a low-dead-time coincidence circuitry is needed to take advantage of the improved efficiency from this technology. The coincidence matching of events coming from different detector modules is performed by an AND-logic on the arriving edges of the module output timing pulses. A flexible modular architecture has been adopted to facilitate the use of the coincidence circuitry for different detector module configurations in addition to different electronic and mechanical implementations. The application of backplane/plug-in architecture and programmable devices (EPLD/FPGA) along with a digital signal processor (DSP) provide reprogrammable flexibility and expandability, allowing scans ranging from animal and breast PET to whole-body PET. There are 42 possible combinations of module pairs derived from the maximum 12 detector modules in coincidence with seven opposite modules. Both the accidental and total (true + accidental) coincidences are simultaneously collected in real time;the accidental timing shift is greater than or equal to200 ns relative to true events. The timing-gate window for the coincidence AND-logic can be dynamically, digitally adjusted during data acquisition between 6.5 and 16 ns to optimize the signal-to-noise ratio in the data. The prototype circuit showed that the timing accuracy is far better than 0.5 ns and the coincidence dead-time is less than 21 ns.

关键词： coincidence circuits digital signal processor positron emission tomography (PET) programmable logic array

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IAPDL-based low-power adiabatic programmable logic array

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MICROELECTRONICS JOURNAL 2000年第4期31卷 235-238页

作者： Lau, KT Liu, F Nanyang Technol Univ Ctr Microelect Sch Elect & Elect Engn Singapore 639798 Singapore

A novel low power programmable logic array structure based on adiabatic switching is presented. Simulation results using HSPICE with 0.8 mu m technology designs show that the power savings of the proposed adiabatic programmable logic array (PLA) circuit is up to 60%, compared to the dynamic PLA circuit. Compared to APDL (Adiabatic Pseudo-Domino logic) PLA, the power saving is about 15% and the device count savings is about 20%. The power saving is improved further at lower supply voltages. At 2 V Vdd and 200 MHz clock frequency, the power saving is about 25% compared to APDL PLA. Compared to static PLA, the power saving is even more significant. HSPICE simulations also show that the proposed PLA can function correctly up to I GHz at 5 V Vdd, and the supply voltage can be scaled down to 2 V at 200 MHz. (C) 2000 Elsevier Science Ltd. All rights reserved.

关键词： adiabatic pseudo-domino logic programmable logic array HSPICE

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PLA-Based regular structures and their synthesis

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2003年第6期22卷 723-729页

作者： Mo, F Brayton, R Univ Calif Berkeley Dept Elect Engn & Comp Sci Berkeley CA 94720 USA

Two regular circuit structures based on the programmable logic array (PLA) are proposed. They provide alternatives to the widely used standard-cell structure and have better predictability and simpler design methodologies. A whirlpool PLA is a cyclic four-level structure, which has a compact layout. Doppio-ESPRESSO, a four-level logic minimization algorithm, is developed for the synthesis of Whirlpool PLAs. A river PLA is a stack of multiple output PLAs, which uses river routing for the interconnections of the adjacent PLAs. A synthesis algorithm for river PLAs uses multilevel logic synthesis, simulated-annealing, and ESPRESSO targeting a combination of minimal area and delay.

关键词： programmable logic array

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PLA-Based regular structures and their synthesis

PLA-Based regular structures and their synthesis

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International Workshop on logic and Synthesis (IWLS)

作者： Mo, F Brayton, R Univ Calif Berkeley Dept Elect Engn & Comp Sci Berkeley CA 94720 USA

关键词： programmable logic array

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Design of multiple-valued programmable logic array with unary function generators

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IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS 1999年第9期E82D卷 1254-1260页

作者： Hata, Y Kamiura, N Yamato, K Himeji Inst Technol Dept Comp Engn Himeji Hyogo 6712201 Japan Hyogo Univ Dept Econ & Informat Sci Kakogawa 6750101 Japan

This paper describes the benefit of utilizing the unary function generators in a multiple-valued programmable logic array (PLA). We will clarify the most suitable PLA structure in terms of the array size. The multiple-valued PLA considered here has a structure with two types of function generators (literal and unary function generators), a first-level array and a second-level array. On investigating the effectiveness to reduce the array size, we can pick up four form PLAs: MAX-of-TPRODUCT form, MIN-of-TSUM-form, TSUM-of-TPRODUCT form and TPRODUCT-of-TSUM form PLAs among possible eight form PLAs constructing from the MAX, MIN, TSUM and TPRODUCT operators. The upper bound of the array sizes with v UGs is derived as ([log(2) p]-p upsilon + p(n - upsilon) + 1) p(n-1) to realize any n-variable p-valued function. Next, experiments to derive the smallest array sizes are done for 10000 randomly generated functions and 21 arithmetic functions. These results conclude that MAX-of-TPRODUCT form PLA is the most useful in reducing the array size among the four form PLAs.

关键词： multiple-valued logic programmable logic array unary function logic design minimization

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River PLAs: a regular circuit structure 02

River PLAs: a regular circuit structure

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Proceedings of the 39th annual Design Automation Conference

作者： Fan Mo Robert K. Brayton University of California Berkeley CA

ISBN: (纸本)9781581134612

A regular circuit structure called a River PLA and its re-configurable version, Glacier PLA, are presented. River PLAs provide greater regularity than circuits implemented with standard-cells. Conventional optimization stages such as technology mapping, placement and routing are eliminated. These two features make the River PLA a highly predictable structure. Glacier PLAs can be an alternative to FPGAs, but with a simpler and more efficient design methodology.

关键词： river routing programmable logic array

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programmable multiplierless digital filter array for embedded SoC applications

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ELECTRONICS LETTERS 2001年第12期37卷 735-737页

作者： Hounsell, BI Arslan, T Univ Edinburgh Dept Elect Engn Edinburgh EH9 3JL Midlothian Scotland

The authors present a novel, programmable logic array for implementing high performance filter functions within embedded system-on-chip platforms. The novelty of the architecture is demonstrated through its specially tailored configurable logic units, and hierarchical routing scheme. The architecture and routing hierarchy are described using a filter example and results are provided demonstrating scalability, speed, and array utilisation using a typical SoC bus specification.

关键词： network routing Digital signal processing chips Microprocessors and microcomputers programmable logic arrays digital signal processing chips digital filters operation speed embedded SoC applications DSP cores Parallel architecture application specific integrated circuits hierarchical routing scheme high performance filter functions SoC bus specification programmable filters embedded systems Digital filters programmable digital filter array Semiconductor integrated circuits routing hierarchy logic circuits logic and switching circuits arrays parallel architectures VLSI programmable logic array multiplierless digital filter array array utilisation scalability embedded system-on-chip platforms

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