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IEEE TRANSACTIONS ON COMPUTERS 2000年第4期49卷 348-359页

作者： Shyu, M Wu, GM Chang, YD Chang, YW Natl Tsing Hua Univ Dept Comp & Informat Sci Hsinchu 300 Taiwan

A switch block M with W terminals on each side is said to be universal if every set of nets satisfying the dimension constraint (i.e., the number of nets on each side of M is at most W) is simultaneously routable through M [2]. In this paper, we present an algorithm to construct N-sided universal switch blocks with W terminals on each side. Each of our universal switch blocks has ((N)(2))W switches and switch-block flexibility N - 1 (i.e., FS = N - 1). We prove that no switch block with less than ((N)(2))W switches can be universal. We also compare our universal switch blocks with others of the topology associated with Xilinx XC4000-type FPGAs. To explore the area performance of the universal switch blocks, we develop a detailed router for hierarchical FPGAs (HFPGAs) with 5-sided switch blocks. Experimental results demonstrate that our universal switch blocks improve routability at the chip level. Based on extensive experiments, we also provide key insights into the interactions between switch-block architectures and routing.

关键词： analysis architecture design digital gate array programmable logic array

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Quasi-universal switch matrices for FPD design

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IEEE TRANSACTIONS ON COMPUTERS 1999年第10期48卷 1107-1122页

作者： Wu, GM Chang, YW Natl Chiao Tung Univ Dept Comp & Informat Sci Hsinchu 300 Taiwan

An FPD switch module M with omega terminals on each side is said to be universal if every set of nets satisfying the dimension constraint (i.e., the number of nets on each side of M is at most omega) is simultaneously routable through M [8]. Chang-et al, have identified a class of universal switch blocks in [8]. In this paper, we consider the design and routing problems for another popular model of switch modules called switch matrices. Unlike switch blocks, we prove that there exist no universal switch matrices. Nevertheless, we present quasi-universal switch matrices which have the maximum possible routing capacities among all switch matrices of the same size and show that their routing capacities converge to those of universal switch blocks. Each of the quasi-universal switch matrices of size omega has a total of only 14 omega - 20 (14 omega - 21) switches if omega is even (odd), omega > 1, compared to a fully populated one which has 3 omega(2) - 2 omega switches. We prove that no switch matrix with less than 14 omega - 20 (14 omega - 21) switches can be quasi-universal. Experimental results demonstrate that the quasi-universal switch matrices improve routabilty at the chip level.

关键词： analysis architecture design digital gate array programmable logic array

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Two-Level logic minimization for low power

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ACM Transactions on Design Automation of Electronic Systems 1999年第1期4卷 52-69页

作者： Itri, Jyh-Mou Tseng Jou, Jing-Yang ITRI Taiwan National Chiao Tung University Taiwan Computer and Communication Research Lab. ITRI Bldg. 14 Chutung Hsinchu 310 195-11 Sec. 4 Chung Hsing Rd Taiwan Department of Electronics Engineering National Chiao Tung University Hsinchu 300 1001 Ta-Hsueh Road Taiwan

In this paper we present a complete Boolean method for reducing the power consumption in two-level combinational circuits. The two-level logic optimizer performs the logic minimization for low power targeting static PLA, general logic gates, and dynamic PLA implementations. We modify the espresso algorithm by adding our heuristics, which bias logic minimization toward lowering power dissipation. In our heuristics, signal probabilities and transition densities are two important parameters. The experimental results are promising. © 1999 ACM.

关键词： logic synthesis Low power design programmable logic array Two-level logic minimization

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Computing support-minimal subfunctions during functional decomposition

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1998年第3期6卷 354-363页

作者： Legl, C Wurth, B Eckl, K Tech Univ Munich Inst Elect Design Automat D-80290 Munich Germany Synopsys Inc Mountain View CA 94043 USA

The growing popularity of look-up table (LUT)-based field programmable gate arrays (FPGA's) has renewed the interest in functional or Roth-Karp decomposition techniques. Functional decomposition is a powerful decomposition method that breaks a Boolean function into a set of subfunctions and a composition function. Little attention has so far been given to the problem of selecting good subfunctions after partitioning the input variables into the disjoint bound and free sets. Therefore, the extracted subfunctions usually depend on all bound variables. In this paper,(1) we present a novel decomposition algorithm that computes subfunctions with a minimal number of inputs. This reduces the number of LUT's and improves the usage of multiple-output SRAM cells. The algorithm iteratively computes subfunctions;in each iteration step it implicitly computes a set of possible subfunctions and finds a subfunction with minimal support, Moreover, our technique finds nondisjoint decompositions, and thus unifies disjoint and nondisjoint decomposition. The algorithm is very fast and yields substantial reductions of the number of LUT's and SRAM cells.

关键词： programmable logic array technology mapping

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Circuit techniques in a 266-MHz MMX-enabled processor

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1997年第11期32卷 1650-1664页

作者： Draper, D Crowley, M Holst, J Favor, G Schoy, A Trull, J BenMeir, A Khanna, R Wendell, D Krishna, R Nolan, J Mallick, D Partovi, H Roberts, M Johnson, M Lee, T Laboratory of Chromatography DEPg.Fac.Quimica Universidad Nacional Autonoma de Mexico Circuito interior Cd Universitaria/CP 04510 Mexico D.F.Mexico

The AMD-K6 MMX-enabled processor is plug-compatible with the industry-standard Socket 7 and is binary compatible with the existing base of legacy X86 software. The microarchitecture is based on an out-of-order, superscalar execution engine using speculative execution, High performance and compact die size are achieved by using self-resetting, self-timed and pulsed-latch circuit design techniques in custom blocks and placed-and-routed blocks of standard cells, The 162 sq, mm die is fabricated on a 0.35-mu m, five-layer metal process with local interconnect, It is assembled into a ceramic pin grid array (PGA) using C4 flip-chip mounting. The processor functions at clock speeds up to 266 MHz.

关键词： cache memories computer architecture design automation software flip-flops integrated circuit design logic design phase-locked loops programmable logic array read only memories

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A DETERMINISTIC BUILT-IN SELF-TEST GENERATOR BASED ON CELLULAR-AUTOMATA STRUCTURES

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IEEE TRANSACTIONS ON COMPUTERS 1995年第6期44卷 805-816页

作者： BOUBEZARI, S KAMINSKA, B Dept. of Electr. Eng. Ecole Polytech. Montreal Que. Canada

This paper proposes a new approach for designing a cost-effective, on-chip, deterministic, built-in, self-test generator. Given a set of precomputed test vectors (obtained by an ATPG tool) with a predetermined fault coverage, a simple test vector generator (TVG) is synthesized to apply the given test set in a minimal test time. To achieve this objective, cellular automata (CA) structures have been used in which the rule space is not limited to the linear rules commonly used in CA studies recently. Based on some new notations and new formulations of CA properties, two techniques are developed to synthesize such a TVG which is used to generate an ordered/unordered deterministic test vector set. The resulting TVG is very efficient in terms of hardware size and speed performance, and is very regular and testable. Simulation of various benchmark combinational circuits has given good results when compared to alternative solutions.

关键词： CELLULAR AUTOMATA TEST VECTOR GENERATOR programmable logic array BUILT-IN SELF-TEST AUTONOMOUS FINITE-STATE MACHINE

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A FAULT MODEL FOR MULTIPLE-VALUED PLAS AND ITS EQUIVALENCES

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IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 1994年第9期E77A卷 1527-1534页

作者： NAGATA, Y MUKAIDONO, M Univ of Ryukyus Okinawa Japan

In this paper, a fault model for multiple-valued programmable logic arrays (MV-PLAs) is proposed and the equivalences of faults of MV-PLA's are discussed. In a supposed multiple-valued NOR/TSUM PLA model, it is shown that multiple-valued stuck-at faults, multiple-valued bridging faults, multiple-valued threshold shift faults and other some faults in a literal generator circuit are equivalent or subequivalent to a multiple crosspoint fault in the NOR plane or a multiple fault of weights in the TSUM plane. These results lead the fact that multiple-valued test vector set which indicates all multiple cross-point fault and all multiple fault of weights also detects above equivalent or subequivalent faults in a MV-PLA.

关键词： EQUIVALENCES OF FAULTS FAULT MODEL MULTIPLE-VALUED logic programmable logic array TEST COMPACTION

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DESIGN OF PSEUDOEXHAUSTIVE TESTABLE PLA WITH LOW OVERHEAD

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IEEE TRANSACTIONS ON COMPUTERS 1993年第7期42卷 887-891页

作者： SHEN, WZ HWANG, GH HSU, WJ JAN, YJ ITRI COMP & COMMUN LABHSINCHUTAIWAN

The pseudoexhaustive testing (PET) scheme is a economic approach to test a large embedded programmable logic array (PIA). In this paper, we propose an efficient algorithm named low overhead PET (LOPET) to partition th... 详细信息

关键词： BUILT-IN SELF-TEST DESIGN FOR TESTABILITY programmable logic array PSEUDOEXHAUSTIVE TESTING

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The OR-k method for on-line checking of programmable logic arrays

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Journal of Electronic Testing 1992年第1期3卷 53-65页

作者： Marcynuk, D.M. Miller, D.M. Department of Computer Science University of Manitoba Winnipeg R3T 2N2 MB Canada Department of Computer Science University of Victoria Victoria V8W 3P6 B.C. Canada

A programmable logic array (PLA) is nonconcurrent if every input pattern selects exactly one product term. We relax this requirement to limited concurrency where all product terms selected by the same input pattern must have identical output parts. A new testing method, OR-k testability, is developed for the on-line (concurrent) checking of limited concurrency PLAs. OR-k testing detects errors due to the selection of one or more extra product terms, and a conventional two-rail parity check on the outputs detects the other errors from single stuck-at, bridging, cross-point and broken line faults. The output patterns of an OR-k testable PLA must be unordered. For such PLAs, certain subsets of the outputs take on an all 1's pattern only in the presence of an extra product term error condition. A limited concurrency PLA tested by OR-k testability is strongly fault secure. © 1992 Kluwer Academic Publishers.

关键词： concurrency fault secure design on-line checking programmable logic array

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BOUNDS ON THE AVERAGE NUMBER OF PRODUCTS IN THE MINIMUM SUM-OF-PRODUCTS EXPRESSIONS FOR MULTIPLE-VALUED INPUT 2-VALUED OUTPUT FUNCTIONS

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IEEE TRANSACTIONS ON COMPUTERS 1991年第5期40卷 645-651页

作者： SASAO, T Dept. of Comput. Sci. & Electron. Kyushu Inst. of Technol. Iizuka Japan Abstract Authors References Cited By Keywords Metrics Similar Download Citation Email Print Request Permissions

A lower bound L(p)(n, u) and an upper bound U(p)(n, u) on S(p)(n, u) are derived, where S(p)(n, u) is the average number of products in minimum sum-of-products expression for p-valued input two-valued output functions, n is the number of the inputs, and u is the number of minterms. The values of S(p)(n, u) are obtained by minimizing randomly generated functions, and they are compared to the calculated values of U(p)(n, u) and L(p)(n, u). The upper bound is based on the minimization results of the functions with fewer variables. The lower bound is based on an assumption, so it is incorrect until the assumption is proven. These bounds are useful for estimating the size of programming logic arrays.

关键词： COMPLEXITY logic MINIMIZATION MULTIPLE-VALUED logic PRIME IMPLICANTS programmable logic array SUM-OF-PRODUCTS EXPRESSION

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