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COMBINING logic MINIMIZATION AND FOLDING FOR PLAS

IEEE TRANSACTIONS ON COMPUTERS 1991年第6期40卷 706-713页

作者： HSU, YC LIN, YL HSIEH, HC CHAO, TH Dept. of Comput. Sci. Tsing Hua Univ. Hsinchu Taiwan

This paper presents an approach that combines logic minimization and folding for PLA's. An efficient algorithm is proposed for optimal bipartite column folding. In the algorithm, we model the PLA personality matrix as a network and the bipartite PLA folding as a partitioning problem of that network. Our folding algorithm is able to find optimal solutions for the benchmarks from the literature. The algorithm also substitutes product terms by their alternatives in order to find the one best suited for folding. We combine this algorithm and a logic minimization algorithm into a folding system. When comparing the results to those by a conventional approach, about one half of the benchmarks show area gain if product-term-alternatives exist.

关键词： BIPARTITE PLA FOLDING logic MINIMIZATION NETWORK PARTITION PERSONALITY MATRIX programmable logic array

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ABSOLUTE MINIMIZATION OF COMPLETELY SPECIFIED SWITCHING-FUNCTIONS

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IEEE TRANSACTIONS ON COMPUTERS 1991年第1期40卷 53-65页

作者： HONG, SJ MUROGA, S UNIV ILLINOIS DEPT COMP SCI URBANA IL 61801 USA

For the automated design of PLA's with a minimum size, we need computationally efficient procedures that can minimize functions of a large number of variables. For such minimization procedures, excessively long processing time and excessively large memory requirement are major problems to overcome. This paper presents a new absolute minimization procedure for standard PLA's with reduced computation time and memory space. The improvement of the procedure, which is based on the decomposition of ratio sets, is mainly due to the detection of all essential prime implicants during the derivation of inclusion functions and also the merger of two separate procedures previously published by Cutler and Muroga [7] into one efficient procedure.

关键词： ABSOLUTE MINIMIZATION BASE INCLUSION FUNCTION MINIMUM SUM PRESENCE FUNCTION programmable logic array RATIO SET

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Investigation into efficient conversion methods between residue and binary systems

Investigation into efficient conversion methods between resi...

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作者： Gilbert, David E. Naval Postgraduate School

学位级别：硕士

Residue number systems (RNS) can efficiently perform addition, subtraction, and multiplication in a parallel and fault tolerant manner. Because of this, they hold significant promise for use in digital signal processing, where high speed arithmetic operators are needed. However, the difficulties in using RNS, such as magnitude comparison between two RNS values, division, and determining overflow or under- flow out of system range, have prevented more widespread use of these systems. This thesis investigates traditional methods to perform comparisons and to propose some new ones. Proposals include residue number system with quotient (RNS-Q), residue number system quotient-on-demand (RNS-QD), and pipelined conversions from tra- ditional RNS to a mixed radix representation. These proposals will be compared with traditional methods with respect to silicon area needed for implementation, speed with which they can be developed, and VLSI techniques utilized to carry out the design.

关键词： residue number systems VLSI ROM programmable logic array

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AREA-OPTIMIZED REGISTERS USING A FOLDED PLA

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IEE PROCEEDINGS-G CIRCUITS DEVICES AND SYSTEMS 1990年第1期137卷 28-32页

作者： HUERTAS, JL QUINTANA, JM AVEDILLO, MJ Departamento de Electrónica y Electromagnetismo Facultad de Fisica Universidad de Sevilla Avda. Reina Mercedes s/n Sevilla 41012 Spain

A method for implementing flip-flops using a folded PLA in a feedback connection is proposed. The new approach is shown to give effective circuits in terms of silicon area.

关键词： programmable logic array logic design circuit layout flip-flops cellular arrays shift registers integrated logic circuits finite state machine synthesis regular array folding chip area-reduction feedback connection folded PLA logic arrays Digital circuits

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Design of multiple-valued programmable logic arrays

Design of multiple-valued programmable logic arrays

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作者： Yong Ha Ko NAVAL POSTGRADUATE SCHOOL

学位级别：硕士

The goal of this thesis is the development of a programmable logic array (PLA) that accepts multiple-valued inputs and produces multiple valued outputs. The PLA is implemented in CMOS and multiple levels are encoded as current. It is programmed by choosing transistor geometries which control the current level at which the PLA reacts to inputs. An example of a 4-valued PLA is shown. As part of this research, a C program was written that produces a PLA layout.

关键词： Multiple-Valued logic Function programmable logic array Circuit Generation Simulation

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3-STEP HEURISTIC ALGORITHM FOR OPTIMAL PLA COLUMN FOLDING

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ELECTRONICS LETTERS 1988年第17期24卷 1088-1090页

作者： YANG, YY KYUNG, CM Department of Electrical Engineering Korea Advanced Institute of Science & Technology Seoul Korea

A three-step heuristic algorithm for PLA column folding is presented, which is significantly faster than the earlier works and provides nearly optimal results. The three steps are (i) Min-Cut partition of vertices in the column intersection graph, (ii) determination of product order using Fiduccia's Min-Net Cut algorithm, and (iii) head-tail pairing for deciding column folding pairs.

关键词： column intersection graph logic circuits three-step heuristic algorithm integrated logic circuits PLA column folding logic design graph theory cellular arrays min-cut partition programmable logic array logic design methods min-net cut algorithm Combinatorial mathematics column folding pairs head-tail pairing Network topology fast near optimal algorithm

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ABOUT FOLDED-PLA AREA AND FOLDING EVALUATION

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INTEGRATION-THE VLSI JOURNAL 1987年第3-4期5卷 193-215页

作者： CAVIGLIA, DD PIURI, V SANTOMAURO, M POLITECN MILAN DEPT ELECTRI-20133 MILANITALY UNIV BRESCIA DEPT IND AUTOMATBRESCIAITALY

This paper deals with PLA folding strategies: in particular, the accurate evaluation of the area used by folded PLA's is presented. Criteria are proposed to choose the best folding strategy among those considered,... 详细信息

关键词： programmable logic array folding strategies folding evaluation

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AN EFFECTIVE ALGORITHM FOR OPTIMAL PLA COLUMN FOLDING

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INTEGRATION-THE VLSI JOURNAL 1987年第3-4期5卷 217-230页

作者： KUO, YS HU, TC UNIV CALIF SAN DIEGO DEPT ELECT ENGN & COMP SCILA JOLLACA 92093

We develop a heuristic algorithm for optimal PLA column folding. The algorithm consists of two parts: First, the column intersection graph associated with the PLA is min-cut partitioned. Then we can consider this folding problem on a bipartite graph. We shall prove two theoretical results which characterize an optimal folding on a bipartite graph. Generalizing these results, we have a heuristic which is both effective in finding optimal solutions and fast enough to handle large PLAs. Test results on this heuristic algorithm will be reported.

关键词： programmable logic array PLA folding column intersection graph folding on bipartite graph min-cut network partitioning

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DERIVATION OF MINIMAL SUMS FOR COMPLETELY SPECIFIED FUNCTIONS

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IEEE TRANSACTIONS ON COMPUTERS 1987年第3期36卷 277-292页

作者： CUTLER, RB MUROGA, S UNIV ILLINOIS DEPT COMP SCI URBANA IL 61801 USA

Some new concepts in switching theory are pre sented. One of these is called an "abridged minterm base." We can use an abridged minterm base instead of the minterm expansion in conventional absolute minimization procedures. Since an abridged minterm base almost always has much fewer minterms than are in the minterm expansion, we can derive an abridged minterm base for many functions for which it is impossible to derive the minterm expansion. This paper also introduces the concept of generalized inclusion function Q(f) and its decomposition theorem Q(g)·Q(h) = Q(g V h). The theorem is very useful.

关键词： Abridged minterm base Petrick function Quine- McCluskey method Tison Method branch-and-bound method inclusion function minimum sum presence function programmable logic array switching theory

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MASHER - AN AUTOMATIC VLSI LAYOUT SYSTEM

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INTEGRATION-THE VLSI JOURNAL 1986年第1期4卷 3-33页

作者： PETERSON, JC SMITH, KF UNIV ARIZONA DEPT COMP SCITUCSONAZ 85721 UNIV UTAH DEPT COMP SCISALT LAKE CITYUT 84112

This paper describes a system for the automatic layout of VLSI circuits designed using Path programmable logic (PPL) methodology. A formal model has been developed which serves as a framework for the manipulation of PPL circuits. This model supports two basic operations: wire folding and wire splitting. User specified constraints guide the PPL layout process. External wires, those which reach outside of the circuit, may be routed to a particular edge, ordered, or placed adjacently. Heuristics are used to select folds. A heuristic has been developed which chooses those folds which place the fewest restrictions on the circuit. The MASHER system has been fully implemented and a number of real circuits have been laid out. Examples are presented comparing MASHER layouts with both hand layouts and other computer generated layouts.

关键词： Design layout VLSI Path programmable logic PPL programmable logic array PLA MASHER silicon compiler cells folding wire splitting NMOS CMOS constraints transformations ordering dynamic splitting graph theory

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