programmable logic arrays are important building blocks of VLSI circuits and systems. The problem of optimizing the silicon area and the performances of large logicarrays are addressed. In particular a general method...
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programmable logic arrays are important building blocks of VLSI circuits and systems. The problem of optimizing the silicon area and the performances of large logicarrays are addressed. In particular a general method is described for compacting a logic array defined as multiple row and column folding and we address the problem of interconnecting a PLA to the outside circuitry. A constrained optimization problem to achieve minimal silicon area occupation with constrained positions of electrical inputs and outputs is defined. A new computer program, PLEASURE is presented. It implements several algorithms for multiple and/or constrained PLA folding.
An on-line algorithm is developed for the location of single cross point faults in a PLA (FPLA). The main feature of the algorithm is the determination of a fault set corresponding to the response obtained for a faile...
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An on-line algorithm is developed for the location of single cross point faults in a PLA (FPLA). The main feature of the algorithm is the determination of a fault set corresponding to the response obtained for a failed test. For the apparently small number of faults in this set, all other tests are generated and a fault table is formed. Subsequently, an adaptive procedure is used to diagnose the fault. Functional equivalence test is carried out to determine the actual fault class if the adaptive testing results in a set of faults with identical tests. The large amount of computation time and storage required in the determination, a priori, of all the fault equivalence classes or in the construction of a fault dictionary are not needed here. A brief study of functional equivalence among the cross point faults is also made.
A new fault model is proposed for the purpose of testing programmable logic arrays. It is shown that a test set for all detectable modeled faults detects a wide variety of other faults. A test generation method for si...
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A new fault model is proposed for the purpose of testing programmable logic arrays. It is shown that a test set for all detectable modeled faults detects a wide variety of other faults. A test generation method for single faults is then outlined. Included is a bound on the size of test sets which indicates that test sets are much smaller than would be required by exhaustive testing. Finally, it is shown that many interesting classes of multiple faults are also detected by the test sets.
We describe two techniques for the minimization of the area of a programmablelogic Array (PLA). Based on the logic functions to be implemented an assignment of the inputs and outputs to the columns of a PLA is determ...
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We describe two techniques for the minimization of the area of a programmablelogic Array (PLA). Based on the logic functions to be implemented an assignment of the inputs and outputs to the columns of a PLA is determined that is especially suited for row segmentation. An upper bound and a lower bound for the number of rows in the segmented PLA are derived. Furthermore, it is shown how the result can be improved upon by the duplication of some of the inputs.
A hardware technique for testing large programmablearrays is presented. The method is based on an appropriate circuit partitioning and on using nonlinear feedback shift registers for test pattern generation. It allow...
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A hardware technique for testing large programmablearrays is presented. The method is based on an appropriate circuit partitioning and on using nonlinear feedback shift registers for test pattern generation. It allows the testing of a PLA within a number of cycles that is a linear function of the number of inputs and product terms. A 8 \times 16 \times 8 PLA is completely tested within 52 cycles; a 16 \times 48 \times 8 PLA requires 132 cycles. The test patterns do not depend on the individual personalization of any PLA. So there is no more need of an extensive fault simulation or test pattern computation. The result is a fast efficient built-in test for PLA-macros, the most promising building blocks of VLSI circuits.
Exploratory MOS programmablelogic array (PLA's) operating up to a clock frequency of 22 MHz have been realized and successfully operated. These PLA's used dynamic logic gates and are built in epitaxial-silico...
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Exploratory MOS programmablelogic array (PLA's) operating up to a clock frequency of 22 MHz have been realized and successfully operated. These PLA's used dynamic logic gates and are built in epitaxial-silicon films on insulators (ESFI) silicon-on-sapphire (SOS) technology. The problems arising with the use of these dynamic gates in a two-stage logic array are discussed and different circuits are presented. The advantage of these circuits, in addition to their high speeds, is reduced power consumption, and the possibility to determine the number of feedback loops when the array is personalized. The features of the circuits are compared with each other with a complete PLA described in an earlier paper (see ibid., vol. SC-10, p.331 (1975)). The results gained from computer simulations agree reasonably well with the experimental results.
The increasing recognition of PLA"s as efficient and viable modules for such purposes as microprogramming and design of sequential controllers has led to a growing interest in the development of optimum fault det...
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The increasing recognition of PLA"s as efficient and viable modules for such purposes as microprogramming and design of sequential controllers has led to a growing interest in the development of optimum fault detection test sets for these modules. It is now well known that a fault type which is unique to PLA"s is the class of contact faults. A single contact fault is the spurious presence or absence of a contact between a row and a column of a PLA. We consider in this paper the problem of determining the capability of complete single contact fault test sets to cover multiple contact faults of PLA"s. Our approach consists of developing a model of PLA"s which allows one to represent a contact fault in a PLA as a stuck-at fault in the model of the PLA. Using this model, it is shown that more than 98 percent of all multiple contact faults of size 8 and less are inherently covered by every complete single contact fault test set in a PLA. Applications of this model to stuck-at fault diagnosis are also discussed.
programmable logic arrays are important building blocks of VLSI circuits and systems. We address the problem of optimizing the silicon area and the performances of large logicarrays. In particular, we describe a gene...
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This paper presents a programmablelogic array (PLA) layered structure composed of single-electron tunneling transistor (SET) devices. In this array bits of information are represented by the presence or absence of si...
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This paper presents a programmablelogic array (PLA) layered structure composed of single-electron tunneling transistor (SET) devices. In this array bits of information are represented by the presence or absence of single electrons at conducting islands. A layer in the array is composed of a SET summing-inverter cell replicated for performing a programmable Boolean operation of its inputs. A number of layers are added on to implement the logic function. We confirm the correct and stable operation of the PLA matrix using a well-known single-electron circuit simulator based on Monte Carlo technique. We then discuss challenges facing SETs and end with conclusions.
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