Multiple Constrained Folding of Programmable Logic Arrays: Theory and Applications

作     者：De Micheli, Giovanni Sangiovanni-Vincentelli, Alberto 

作者机构：Department of Electrical Engineering and Computer Science University of California Berkeley CA 94720 United States 

出 版 物：《IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems》 (IEEE Trans Comput Aided Des Integr Circuits Syst)

年 卷 期：1983年第2卷第3期

页      面：151-167页

学科分类：0808[工学-电气工程] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 0835[工学-软件工程] 0811[工学-控制科学与工程] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

主　　题：Programmable logic arrays Constraint theory Logic arrays Logic circuits Very large scale integration Silicon Logic design Circuits and systems Constraint optimization Equations 

摘      要：Programmable logic arrays are important building blocks of VLSI circuits and systems. We address the problem of optimizing the silicon area and the performances of large logic arrays. In particular, we describe a general method for compacting a logic array defined as multiple row and column folding and we address the problem of interconnecting a PLA to the outside circuitry. We define a constrained optimization problem to achieve minimal silicon area occupation with constrained positions of electrical inputs and outputs. We present a new computer program, PLEASURE, which implements several algorithms for multiple and/or constrained PLA folding.© 1983 IEEE. All rights reserved.