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Germanium Nanowire reconfigurable transistor Model for Predictive Technology Evaluation

IEEE TRANSACTIONS ON NANOTECHNOLOGY 2022年 21卷 728-736页

作者： Quijada, Jorge Navarro Baldauf, Tim Rai, Shubham Heinzig, Andre Kumar, Akash Weber, Walter M. Mikolajick, Thomas Trommer, Jens NaMLab gGmbH D-01187 Dresden Germany Univ Appl Sci Dresden D-01069 Dresden Germany Univ Appl Sci Dresden D-01069 Dresden Germany Univ Appl Sci Dresden D-01069 Dresden Germany Tech Univ Dresden Chair Processor Design Ctr Adv Elect Dresden D-01169 Dresden Germany Tech Univ Dresden Chair Nanoelect D-01187 Dresden Germany TU Wien Inst Solid State Elect A-1040 Vienna Austria NaMLab gGmbH D-01187 Dresden Germany Tech Univ Dresden Chair Nanoelect D-01187 Dresden Germany

reconfigurable Field Effect transistors can be electrostatically programmed to p- or n-type behavior. This device level reconfigurability is a promising way to enhance the functionality of digital circuits. Here, we present a Verilog-A based Germanium nanowire table model for the analysis of dynamically reconfigurable logic gates. The model is based on TCAD simulations of a nanowire transistor design with feature sizes compatible to a 14nm FinFET process. To showcase that our model enables digital circuit design for reconfigurable operation, performance and power consumption estimations for basic static as well as reconfigurable logic cells are given. Performance improvements over Silicon nanowire based designs are predicted, making Germanium RFETs a promising candidate for future co-integration into standard CMOS processes.

关键词： Functionally enhanced logic gates germanium MIGRFET reconfigurable transistor RFET TIGFET

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A reconfigurable Ge transistor Functionally Diversified by Negative Differential Resistance

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IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY 2024年 12卷 541-547页

作者： Fuchsberger, Andreas Wind, Lukas Nazzari, Daniele Dobler, Alexandra Aberl, Johannes Navarrete, Enrique Prado Brehm, Moritz Vogl, Lilian Schweizer, Peter Lellig, Sebastian Maeder, Xavier Sistani, Masiar Weber, Walter M. Tech Univ Wien Inst Solid State Elect A-1040 Vienna Austria Johannes Kepler Univ Linz Inst Semicond & Solid State Phys A-4040 Linz Austria Univ Calif Berkeley Dept Mat Sci & Engn Berkeley CA 94720 USA Swiss Fed Labs Mat Sci & Technol Lab Mech Mat & Nanostruct CH-8600 Dubendorf Switzerland

A promising approach to advance electronics beyond static operations is to enhance state-ofthe- art systems by the functional diversification of transistors. Here, we experimentally demonstrate that an ultra-thin Ge channel implemented on a Si on insulator platform enables run-time switchable symmetric pand n-type field-effect transistor operability as well as the prominent feature of distinct room-temperature negative differential resistance. Temperature dependent bias spectroscopy is utilized to map electronic transport in these so called negative differential resistance mode reconfigurable transistors. Thereof, a profound understanding of the involved transport physics and electrostatic gating mechanisms is obtained and evaluated. Further, we show that a multi-gate negative differential resistance reconfigurable transistor can effectively replace a cascode of negative differential resistance devices, contributing to a smaller area footprint, and reduced latency of critical paths. Notably, the experimentally obtained multi-heterojunction transistors constitute the first chip-scale platform that combines efficient polarity control as well as sizeand energy-efficient room-temperature negative differential resistance, providing an inherent component of emerging neuromorphic computing.

关键词： Germanium transistors Silicon Logic gates Resistance Spectroscopy Electron devices metal-semiconductor heterojunction reconfigurable transistor negative differential resistance

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Exploring the potential of FinFET transistor technology in reconfigurable logic gates for enhanced computing performance

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JOURNAL OF THE KOREAN PHYSICAL SOCIETY 2024年第12期85卷 1032-1040页

作者： Heydari, Hamid Reza Ahangari, Zahra Nematian, Hamed Kafoori, Kian Ebrahim Islamic Azad Univ Yadegar e Imam Khomeini RAH Shahr e Rey Branch Dept Elect Tehran Iran

Advanced logic gates and transistor technologies play a crucial role in the design of high-speed computing systems. In this paper, a novel 3-dimensional fin-shaped reconfigurable transistor is presented, which exhibits identical behavior in both n-enhancement mode and p-enhancement mode operations. The key highlight of this reconfigurable transistor lies in its ability to integrate XNOR, NOT, and AND gates within a single device. Unlike conventional reconfigurable transistors, the proposed device incorporates a dual-doped n+/p+ source and a Schottky drain region. Notably, this device only requires a control gate, while the drain electrode serves the dual purpose of being the output and program gate. The findings demonstrate remarkable performance characteristics for the n-enhancement mode and p-enhancement mode operations. Specifically, the on-state current is measured to be 3.68 mu A and 2.85 mu A, with corresponding on/off current ratios of 11.25 x 108 and 1.23 x 108, respectively. Moreover, the device achieves a subthreshold swing of 61 mV/dec and 63 mV/dec for the n-enhancement mode and p-enhancement mode, respectively. This innovative design highlights the potential of utilizing a single FinFET reconfigurable transistor to design complex logic gates, demonstrating a significant advancement in integrated circuit technology towards enhanced efficiency and versatility.

关键词： reconfigurable transistor Schottky barrier transistor FinFET Logic gate

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Side-Gate BN-MoS2 transistor for reconfigurable Multifunctional Electronics

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ADVANCED ELECTRONIC MATERIALS 2024年第2期10卷

作者： Zeng, Daobing Ding, Rongxiang Liu, Guanyu Lu, Huihui Zhang, Miao Xue, Zhongying Tian, Ziao Di, Zengfeng Chinese Acad Sci Shanghai Inst Microsyst & Informat Technol Natl Key Lab Mat Integrated Circuits Shanghai 200050 Peoples R China Univ Chinese Acad Sci Ctr Mat Sci & Optoelect Engn Beijing 100049 Peoples R China

Developing 2D reconfigurable multifunctional devices is of great potential in further miniaturizing the chip area and simplifying circuit design. 2D van der Waals (vdW) heterostructures offer a novel approach to realizing reconfigurable multifunctional devices. Despite the numerous previous reports that have integrated various functions in a single 2D heterostructures device, most of those devices are based on a complex multilayer heterostructure or an air-unstable channel material, limiting their ability to be applied in integrated circuits. There is an urgent need to develop 2D reconfigurable multifunctional devices that have a simple structure and stable electrical properties. In this work, a side-gate reconfigurable device is illustrated based on simple BN-MoS2 vdW heterostructures. Three different functions in a single device have been achieved, including a diode, double-side-gate reconfigurable logic transistor, and top floating gate memory. A lateral n(+)-n homojunction is created along the MoS2 channel and the rectification ratio is above 10(5). reconfigurable logic operations (OR, AND) can be achieved in a single double-side-gate device and the current on/off ratio is approximate to t 10(4). Moreover, the device can act as a floating gate memory under back gate operation. Those results pave the way for integrating the same reconfigurable multifunctional devices to realize complex electronic systems.

关键词： floating gate memory MoS2 reconfigurable transistor rectification side gate

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Impact of Geometrical and Process Design Parameters on the Performance of Schottky Barrier reconfigurable Field Effect transistor 5

Impact of Geometrical and Process Design Parameters on the P...

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5th Iranian International Conference on Microelectronics (IICM)

作者： Heydari, Hamid Reza Ahangari, Zahra Nematian, Hamed Kafoori, Kian Ebrahim Islamic Azad Univ Shahr e Rey Branch Yadegar e Imam Khomeini RAH Dept Elect Tehran Iran

ISBN: (纸本)9798350360196

In this study, the electrical properties of a Schottky Barrier reconfigurable Field Effect transistor (SBRFET) are thoroughly evaluated with the variation of important design parameters. The device proposed in this study operates in both n-type and p-type modes by exploiting electrical doping rather than additional physical doping. One of the critical design parameters is the gate work function, which significantly affects the charge density in the channel and subsequently alters the tunneling rate. The findings reveal that gate length variation has a negligible impact on the device's performance. The device achieved an on/off current ratio of 2x10(7) and a subthreshold swing of 87.5 mV/dec for ntype operation, while for p-type operation, it achieved an on/off current ratio of 1.5x10(6) with a subthreshold swing of 95.7 mV/dec. The results of this study pave the way for developing high-speed, low-power digital circuits with reprogrammable logic.

关键词： reconfigurable transistor Schottky Barrier transistor Direct Tunneling Thermionic Emission

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reconfigurable Mixed-Dimensional transistor With Semimetal CNT Contacts

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ADVANCED ELECTRONIC MATERIALS 2025年第8期11卷

作者： Li, Xuanzhang Li, Yuheng Mei, Zhen Liang, Liang Li, Qunqing Fan, Shoushan Wei, Yang Tsinghua Univ Dept Phys State Key Lab Low Dimens Quantum Phys Beijing 100084 Peoples R China Tsinghua Univ Tsinghua Foxconn Nanotechnol Res Ctr Beijing 100084 Peoples R China China Res & Dev Acad Machinery Equipment Beijing 100089 Peoples R China Frontier Sci Ctr Quantum Informat Beijing 100084 Peoples R China

reconfigurable low-dimensional devices are attractive for electronics in the post-Moore era. However, their performance and function design are limited by the metal-semiconductor contacts for the Fermi level pinning and fixed Schottky barrier height (SBH). Here, semimetal carbon nanotube (sCNT) contacts are incorporated into a WSe2 transistor to address these issues. The transistor exhibits excellent ambipolar transfer characteristics with on/off ratio exceeding 107 for both hole and electron conduction. Furthermore, the output characteristics are reconfigured among the four equivalent modes, P-P, P-N, N-P, and N-N, by applying appropriate gate voltage. The significant forward and backward rectifying behaviors at P-N and N-P modes are highly symmetrical and have high rectification ratios of over 106. The improvements are attributed to specific semimetal contacts for the gate-tunable SBH and the drain-induced Schottky barrier lowering (DISBL) effect. Practical circuits include a reconfigurable filter circuit and a logic invertor have been further demonstrated successfully. The progress reveals that the semimetal contacts have great potential in future reconfigurable devices and circuits.

关键词： carbon nanotubes reconfigurable transistor semimetal two-dimensional material

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Realization of a Complementary Full Adder Based on reconfigurable transistors

IEEE ELECTRON DEVICE LETTERS

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IEEE ELECTRON DEVICE LETTERS 2024年第4期45卷 724-727页

作者： Wind, Lukas Maierhofer, Moritz Fuchsberger, Andreas Sistani, Masiar Weber, Walter M. TU Wien Inst Solid State Elect A-1040 Vienna Austria

Fine grain reconfigurability carried out at the transistor level, i.e. the ability to switch between n- and p-type operation, offers new possibilities for highly efficient logic gates. In particular, XOR- and Majority gate circuit implementations can considerably benefit from reconfigurable transistors, as they require less than half of the transistor count needed in conventional static CMOS technology. Using a total of eight highly on-state symmetric reconfigurable field effect transistors fabricated from monolithic Al-Si heterostructures, we experimentally demonstrate a fully functional full adder, a fundamental circuit for many arithmetic applications. The two slightly adapted reconfigurable XOR gates for sum and carry output provide a full output voltage swing using only a single symmetric supply rail, while achieving very low static power consumption due to complementary circuit design and inherent leakage suppression of the devices. Furthermore, their stable operation against input voltage variations is demonstrated with static and transient measurements.

关键词： Full adder reconfigurable transistor RFET silicon on insulator XOR

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Multifunctional Logic-in-Memory Circuits Based on reconfigurable WSe2 transistors via Enhanced Ambipolarity

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ACS NANO 2025年第20期19卷 19442-19453页

作者： Ying, Haoting Xie, Kanghao Cai, Hecheng Li, Zishun Liu, Lin Guo, Xudong An, Minghao Shang, Hongpeng Zheng, Xiaorui Zhejiang Univ Hangzhou 310027 Zhejiang Peoples R China Westlake Univ Sch Engn Zhejiang Key Lab Micro Nano Fabricat & Characteriz Hangzhou 310030 Zhejiang Peoples R China Westlake Inst Optoelect Hangzhou 311421 Zhejiang Peoples R China Westlake Univ Res Ctr Ind Future Hangzhou 310030 Zhejiang Peoples R China

Ambipolar two-dimensional semiconductors exhibit electrostatically modulable carrier polarity, enabling reconfigurable electronic functionalities critical for the development of logic-in-memory computing architectures. However, the ambipolar conduction is generally weak and unbalanced, in particular, under ambient operating conditions. Here, we develop a universal nonvolatile and reconfigurable device architecture based on tungsten diselenide (WSe2) and delicately enhance its ambipolar transport via scanning probe lithography, demonstrating on/off current ratios approaching 1010 for both electron and hole conductions. By integrating floating-gate architecture and split-gate control, the WSe2 device can be configured into memory, transistor, and diode modes and perform reconfigurable linear and nonlinear logic operations with only one device, such as NAND, AND, OR, NOR, XOR, and XNOR circuits. Eventually, we realize operational logic-in-memory circuits by integrating our WSe2 devices on a printed circuit board, demonstrating reliable half adder and parity-checker circuit operations under ambient conditions.

关键词： ambipolar 2D semiconductors well-balanced scanning probe lithography reconfigurable transistor multifunctional logic-in-memorycircuits

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reconfigurable Si Field-Effect transistors With Symmetric On-States Enabling Adaptive Complementary and Combinational Logic

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IEEE TRANSACTIONS ON ELECTRON DEVICES 2024年第2期71卷 1302-1307页

作者： Wind, Lukas Fuchsberger, Andreas Demirkiran, Ozgur Vogl, Lilian Schweizer, Peter Maeder, Xavier Sistani, Masiar Weber, Walter M. TU Vienna Inst Solid State Elect A-1040 Vienna Austria Swiss Fed Labs Mat Sci & Technol Lab Mech Mat & Nanostruct CH-3602 Thun Switzerland

reconfigurable field-effect transistors (RFETs), combining n-and p-type operation in a single device, have already shown promising simulation results for enhancing performance and functionality in conventional devices and further enabling novel adaptive computing concepts. With recent advances in the formation of high-quality monolithic and single-crystalline Al-Si Schottky contacts providing a reproducible way to fabricate RFETs with highly symmetric n-and p-type operation, we are now able to demonstrate their integration in fundamental complementary and combinational logic circuits. In this regard, we show an inverter, as well as NAND/NOR and XOR/XNOR gates, capable of dynamically run-time switching their operation mode, while simultaneously reducing transistor count compared to conventional circuits with static transistors. Importantly, we could demonstrate their reliable operation using only fully symmetric supply voltages while providing a full output swing. Their robust operation is verified by analyzing their noise margins, stability to input voltage variations, and transient behavior. Most notably, the presented device concept and the Al-Si material system are potentially compatible with the state-of-the-art complementary metal-oxide-semiconductor (CMOS) processing technology, paving the way for future hybrid reconfigurable-CMOS circuits with improved functional density and energy efficiency.

关键词： Combinational logic reconfigurable field-effect transistors (RFETs) reconfigurable transistor Schottky barrier field-effect transistor (SBFET) silicon-on-insulator (SOI)

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Nanoscale reconfigurable Si transistors: From Wires to Sheets and Unto Multi-Wire Channels

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ADVANCED ELECTRONIC MATERIALS 2024年第2期10卷

作者： Wind, Lukas Behrle, Raphael den Hertog, Martien I. Murphey, Corban G. E. Cahoon, James F. Sistani, Masiar Weber, Walter M. TU Wien Inst Solid State Elect A-1040 Vienna Austria Inst Neel CNRS F-38042 Grenoble France Univ N Carolina Dept Chem Chapel Hill NC 27599 USA

In this work, bottom-up Al-Si-Al nanowire (NW) heterostructures are presented, which act as a prototype vehicle toward top-down fabricated nanosheet (NS) and multi-wire (MW) reconfigurable field-effect transistors (RFETs). Evaluating the key parameters of these transistors regarding the on- and off-currents as well as threshold voltages for n- and p-type operation exhibit a high degree of symmetry. Most notably also a low device-to-device variability is achieved. In this respect, the investigated Al-Si material system reveals its relevance for reconfigurable logic cells obtained from Si NSs. To show the versatility of the proposed devices, this work reports on a combinational wired-AND gate obtained from a multi-gate RFET. Additionally, up-scaling the current is achieved by realizing a MW RFET without compromising reconfigurability. The Al-Si-Al platform has substantial potential to enable complex adaptive and self-learning combinational and sequential circuits with energy efficient and small footprint computing paradigms as well as for native components for hardware security circuits. The applicability of monolithic Al-Si heterojunctions for reconfigurable transistors is demonstrated on bottom-up grown Si nanowires. To enable multi-gate and multi-channel devices for combinational wired-logic and for efficient current up-scaling a transfer to SOI technology is reported. The proposed Al-Si platform might be promising for diverse adaptive self-learning computing as well as new approaches for hardware security ***

关键词： combinational logic reconfigurable transistor RFET SBFET silicon on insulator

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