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FAST PROTECTION-DOMAIN CROSSING IN THE CHERI CAPABILITY-SYSTEM ARCHITECTURE

IEEE MICRO 2016年第5期36卷 38-49页

作者： Watson, Robert N. M. Norton, Robert M. Woodruff, Jonathan Moore, Simon W. Neumann, Peter G. Anderson, Jonathan Chisnall, David Davis, Brooks Laurie, Ben Roe, Michael Dave, Nirav H. Gudka, Khilan Joannou, Alexandre Markettos, A. Theodore Maste, Ed Murdoch, Steven J. Rothwell, Colin Son, Stacey D. Vadera, Munraj Univ Cambridge Comp Lab Cambridge CB2 1TN England Univ Cambridge Comp Lab Comp Engn Cambridge CB2 1TN England SRI Int Comp Sci Lab Menlo Pk CA USA Mem Univ Dept Elect & Comp Engn St John NF Canada Univ Cambridge Cambridge CB2 1TN England SRI Int Menlo Pk CA USA Google London England Univ Cambridge Secur Grp Comp Lab Cambridge CB2 1TN England UCL Informat Secur Res Grp London WC1E 6BT England

Capability hardware enhanced risc instructions (cheri) supplement the memory management unit (mmu) with instruction-set architecture (isa) extensions that implement a capability-system model in each address space. The authors propose isa support for sealed capabilities, hardware-assisted checking during protection-domain switching, a lightweight capability flowcontrol model, and fast register clearing, while retaining the flexibility of a software-defined protection-domain transition model.

关键词： reduced instruction set computing Storage Management Chips Fast Protection Domain CHERI Capability System Architecture Capability Hardware Enhanced RISC instructions Conventional Memory Management Unit MMU instruction set Architecture ISA Hardware Software Object Capability Model Memory Sharing Flow Control Model Software Defined Protection Domain Transition Model Memory Management Systems Modeling reduced instruction set computing Program Processors Capability Engineering Memory Management Unit instruction set Architecture ISA Processor Security Memory Protection Capability CHERI Hardware Software Compartmentalization Vulnerability Mitigation Capability System Capabilities

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USING CAD TOOLS IN THE DESIGN OF CRISP

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IEEE DESIGN & TEST OF COMPUTERS 1987年第3期4卷 21-31页

作者： DITZEL, DR BERENBAUM, AD AT&T BELL LABS INFORMAT MICROSYST LABHOLMDELNJ 07733

CRISP is a high-performance 32-bit RISC microprocessor that uses 172,163 transistors in a 1.75?m CMOS technology. The largechip size of 10.35 mmx 12.23 mm and complexity of the design required an extensive top-down approach in a set of integrateddesign tools. CAD tools ranged from an instruction set interpreter to detailed timing simulation. Practical problems encounteredinclude communication among different tools and limits on process size, file size, and total compute time. Use of both symboliccompaction and physical layout, while improving initial efficiency, created problems later in the design.

关键词： Design automation Decoding Microprocessors CMOS technology Information systems reduced instruction set computing Timing Computational modeling Compaction Hardware

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Fine-grained hardware switching scheme for power reduction in multiplication

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ELECTRONICS LETTERS 2016年第16期52卷 1374-1375页

作者： Huang, Y. Li, C. Li, M. Van der Perre, L. Dehaene, W. IMEC Leuven Belgium Katholieke Univ Leuven ESAT Dept Leuven Belgium

This Letter presents a fine-grained hardware switching scheme to choose from the proper hardware for low power computing. It exploits the word-length optimisation opportunities for multiplication unit. With the proposed technique, the gate-level simulation result on OpenRISC shows 23.7% power reduction for the multiplication unit, which accounts for 9.5% power reduction for its execution unit.

关键词： reduced instruction set computing low power computing multiplication unit gate-level simulation low-power electronics word-length optimisation opportunities fine-grained hardware switching scheme execution unit power reduction OpenRISC Computer architecture

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INDUSTRIAL ELECTRONICS

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IEEE SPECTRUM 1991年第1期28卷 59-60页

作者： KAPLAN, G IEEE Spectrum New York NY USA

Progress in industrial electronics during 1990 is reviewed. Fuzzy logic, intelligent control, and computer-integrated manufacturing (CIM) are improving manufacturing flexibility and reducing costs. At the same time, advanced computer numerical control (CNC) based on a reduced-instruction-set computer (RISC) chip is expected to sharpen precision in high-speed machining. There were notable advances toward an open system architecture for programmable controllers and machine vision systems. An X-ray laminography system for inspecting the solder joints on printed-circuit boards, particularly those of surface-mounted components, with 25 mu m resolution became available.< >

关键词： Industrial electronics Computer integrated manufacturing Computer numerical control Fuzzy logic Intelligent control Computer aided manufacturing Costs Time sharing computer systems reduced instruction set computing Machining

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NEW FFT BIT-REVERSAL ALGORITHM

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IEEE TRANSACTIONS ON SIGNAL PROCESSING 1995年第4期43卷 991-994页

作者： RIUS, JM DEPORRATADORIA, R Antennas Microwave and Radar GroupDepartment Teoria del Senyal i Comunicacions Universitat Politecnica de Catalunya Barcelona Spain

This correspondence presents a very short, simple, easy to understand bit-reversal algorithm for radix-2 fast Fourier transform (PPT), which is, furthermore, easily extendable to radix-M. In addition, when implemented... 详细信息

关键词： Signal processing algorithms Radar antennas Fast Fourier transforms Microwave antennas Counting circuits reduced instruction set computing Assembly

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A 600-MHz superscalar floating-point processor

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1999年第7期34卷 1026-1029页

作者： Clouser, J Matson, M Badeau, R Dupcak, R Samudrala, S Allmon, R Fairbanks, N Compaq Comp Corp Shrewsbury MA 01545 USA

The floating-point unit of a 600-MHz, out-of-order, superscalar RISC Alpha microprocessor is described. The unit achieves 59 SpecFP95 and can transfer register data at up to 9.6 GB/s, It has two independent pipelines for multiply and add/subtract operations, with iterative divide and square-root circuits, and is fabricated in a 2.2-V, 0.35-mu m CMOS process.

关键词： Clocks Registers Circuits Pipeline processing Energy consumption Delay effects Out of order reduced instruction set computing Microprocessors CMOS process

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Exploiting Direct Memory Operands in GPU instructions

IEEE COMPUTER ARCHITECTURE LETTERS

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IEEE COMPUTER ARCHITECTURE LETTERS 2024年第2期23卷 162-165页

作者： Mohammadpur-Fard, Ali Darabi, Sina Falahati, Hajar Mahani, Negin Sarbazi-Azad, Hamid Sharif Univ Technol Dept Comp Engn Tehran 111559466 Iran Inst Res Fundamental Sci IPM Sch Comp Sci Tehran 195383351 Iran Univ Svizzera Italiana USI Fac Informat CH-6900 Lugano Switzerland Barcelona Supercomp Ctr BSC Barcelona 08034 Spain Shahid Bahonar Univ Dept Comp Engn Higher Educ Complex Zarand Kerman 761691411 Iran

GPUs are widely used for diverse applications, particularly data-parallel tasks like machine learning and scientific computing. However, their efficiency is hindered by architectural limitations, inherited from historical RISC processors, in handling memory loads causing high register file contention. We observe that a significant number (around 26%) of values present in the register file are typically used only once, contributing to more than 25% of the total register file bank conflicts, on average. This paper addresses the challenge of single-use memory values in the GPU register file (i.e. data values used only once) which wastes space and increases latency. To this end, we introduce a novel mechanism inspired by CISC architectures. It replaces single-use loads with direct memory operands in arithmetic operations. Our approach improves performance by 20% and reduces energy consumption by 18%, on average, with negligible (<1%) hardware overhead.

关键词： Registers Graphics processing units Computer architecture reduced instruction set computing Arithmetic Hardware Standards CISC GPGPU RISC register file

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DESIGN OF AN RSFQ MICROPROCESSOR

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IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY 1995年第2期5卷 3325-3328页

作者： BUNYK, P SEMENOV, VK Department of Physics State University of New York Stony Brook Stony Brook NY USA

We are discussing a general-purpose microprocessor architecture that is suitable for implementation using the Rapid Single-Flux-Quantum (RSFQ) family of logic-memory circuits. While the microprocessor provides a functionally complete RISC instruction set with 16-bit words, a bit-serial self-timed approach makes it simple enough to be fabricated using the current Josephson junction technology. Our plans are to design, fabricate and test a completely operational prototype of this system.

关键词： Microprocessors Josephson junctions Clocks Pipelines Frequency reduced instruction set computing Physics Circuit testing System testing Prototypes

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THE ARCHITECTURE OF A PROCESSOR ARRAY FOR VIDEO DECOMPRESSION

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IEEE TRANSACTIONS ON CONSUMER ELECTRONICS 1993年第3期39卷 565-569页

作者： MAYER, AC SIEMENS AG CORP RES & DEVMUNICHGERMANY

Different standards for video compression demand a flexible approach for integrating this functionality into multimedia terminals and computers. In this paper a programmable processor array (RISC, dataflow, four processor elements) and the corresponding decoding software is presented for this task. The results show, that this kind of architecture is efficient and its expense can be compared with other implementations.

关键词： Computer architecture Hardware Memory management Video compression reduced instruction set computing Registers Transform coding Software algorithms Research and development Tin

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SOLID-STATE

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IEEE SPECTRUM 1992年第1期29卷 42-&页

作者： WATSON, GF IEEE Spectrum New York NY USA

reduced-instruction-set computer (RISC) architecture entrenched itself more deeply in 1991. Embedded microcontrollers reached new levels of integration, became easier to program, and attained even greater acceptance as embedded components. Explosive growth was seen in field-programmable gate arrays. Digital signal processors are being embedded in modems, speech recognition equipment, and other telecommunications products. Most chip suppliers are preparing chips for a shift in power supply voltage from the usual 5 V to 3.3 V or less. The cost of manufacturing systems continued its exponential rise.< >

关键词： Telecommunication computing reduced instruction set computing Computer architecture Microcontrollers Explosives Field programmable gate arrays Digital signal processors Modems Speech recognition Power supplies

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