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On-Chip Relative Single-Event Transient/Single-Event Upset Susceptibility test circuit for Integrated circuits Working in Real Time

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2018年第1期65卷 376-381页

作者： Hao, Peipei Chen, Shuming Wu, Zhenyu Chi, Yaqing Natl Univ Def Technol Coll Comp Changsha 410073 Hunan Peoples R China Natl Univ Def Technol Natl Lab Paralleling & Distributed Proc Changsha 410073 Hunan Peoples R China

With technology scaling down, scale of the integrated circuit (IC) increases rapidly. It is unrealistic to harden every element in the IC, hence it is critical to evaluate relative single-event transient (SET) or single-event upset (SEU) sensitivity of each node in the IC to selectively harden the elements connected to the identified highly sensitive nodes. Therefore, this paper proposes a test circuit to measure the relative SET/SEU sensitivity of each node in any circuit working in real time. This will have significant implications for designing ICs with high reliability and low overheads.

关键词： Highly reliable integrated circuit low overhead relative susceptibility single-event transient (SET) single-event upset (SEU) test circuit

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Full-Power test of HVDC circuit-Breakers With AC Short-circuit Generators Operated at Low Power Frequency

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IEEE TRANSACTIONS ON POWER DELIVERY 2019年第5期34卷 1843-1852页

作者： Belda, Nadew Adisu Plet, Cornelis Arie Smeets, Rene Peter Paul DNV GL KEMA Labs NL-6812 Arnhem Netherlands

This paper provides a pragmatic solution to the challenge of testing fault current interruption of high-voltage direct current (HVDC) circuit breakers (CBs). The critical parameters in the design of a test circuit capable of supplying the necessary stresses: current, energy, and voltage (both during and after interruption) are discussed. In addition, a practical implementation of a test circuit based on ac short-circuit generators operated at low power frequency, which is capable of testing the current interruption performance of the proposed technologies of HVDC CBs, is discussed. tests validating the proposed method and circuit have been conducted on a prototype of an HVDC CB and the test results are presented. Since the performance of some technologies of HVDC CBs can depend on the magnitude of the interrupted current, four test duties are defined and demonstrated in the paper. Moreover, testing of HVDC CBs using ac short-circuit generators poses new challenges, such as the application of dielectric dc stress after current interruption and the protection of both the test-object as well as the test-circuit components when the HVDC CB fails to interrupt. Methods to overcome these challenges are developed and practically demonstrated in a test laboratory. Finally, taking into account the available resources of the author's test laboratory, the capability to test multiple series-connected modules of different technologies of HVDC CBs is verified and example cases are demonstrated. Six short-circuit generators (13 500 MVA @ 50 Hz) and up to ten step-up transformers (up to 550 kV) were actually used.

关键词： HVDC circuit-breakers HVDC short-circuit tests HVDC transmission multi-terminal test circuit testing

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test circuit for MMC-based VSC valves in HVDC power station

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ELECTRONICS LETTERS 2017年第4期53卷 272-273页

作者： Jung, J. -H. Nho, E. -C. Chung, Y. -H. Baek, S. -T. Lee, J. -H. Pukyong Natl Univ Dept Elect Engn Busan 48513 South Korea HVDC Res Grp LS Ind Syst Gyeonggi Do 14119 South Korea

A test circuit for modular multilevel converter (MMC)-based voltage-sourced converter valves in high-voltage direct current (HVDC) system is dealt with. The proposed scheme has an ability to provide a submodule current having DC component as well as AC component to represent real operating condition of HVDC transmission system. There is no need of extra power supply to provide the DC current component because the scheme has inherent circulating DC current between rectifier and inverter valves. Therefore, only one small power rated DC power supply is necessary. Experiments are carried out to show the validity of the proposed test circuit.

关键词： HVDC power transmission HVDC power convertors voltage-source convertors rectifier substations invertors HVDC power station test circuit modular multilevel converter-based VSC valve MMC-based voltage sourced converter valve high-voltage direct current system AC component HVDC transmission system DC current component inverter valve rectifier valve DC power supply

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Reconfigurable Large-Current and High-Voltage test Bench for HVDC circuit Breaker Verification

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IEEE TRANSACTIONS ON POWER ELECTRONICS 2023年第1期38卷 523-537页

作者： Krneta, Nikola Hagiwara, Makoto Tokyo Inst Technol Dept Elect & Elect Engn Tokyo 1528552 Japan

This article presents a novel circuit configuration of a high-voltage direct current circuit breaker (HVdcCB) test bench that is based on a modified H-bridge modular multilevel cascaded converter (MMCC). The modified MMCC is composed of fewer H-bridge cells, and it can be reconfigured during operation to allow the proposed test bench to output large current or high voltage for the current breaking and dielectric withstand tests. Although simultaneous output of large current and high voltage is not possible, the maximum transient interrupt voltage (TIV) withstand test can be performed with reduced ratings. The controllable output allows generation of complex waveforms to simulate a wide range of fault conditions. Furthermore, the modified MMCC has some inherent safety features that can reduce the need for additional protective equipment in case of operational failure of the HVdcCB. In contrast, the conventional charged capacitor and inductor-based designs cannot generate arbitrary waveforms, are only suitable for current breaking tests, and require additional circuits to generate initial conditions for the HVdcCB. AC short-circuit generator-based designs offer one degree of freedom for control of the output waveforms and can sustain the maximum TIV withstand test. However, the ac output is unsuitable for the dielectric withstand test, and additional circuits are required to provide initial conditions for the HVdcCB. The proposed test bench circuit configuration is verified using a downscaled experimental test bench that consists of a total of nine H-bridge cells with an equivalent switching frequency of 92.5 kHz.

关键词： circuit faults HVDC transmission testing Capacitors Inductors Dielectrics Switches DC circuit breaker high-voltage direct current (HVdc) high-voltage direct current circuit breaker (HVdcCB) modular multilevel cascaded converter (MMCC) test bench test circuit

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Design and Analysis of a Novel HVDC circuit Breaker test Bench Based on an H-Bridge Cell MMCC

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IEEE ACCESS 2022年 10卷 75789-75801页

作者： Krneta, Nikola Hagiwara, Makoto Tokyo Inst Technol Dept Elect & Elect Engn Tokyo 1528552 Japan

This paper proposes a novel circuit configuration for a high-voltage direct-current circuit breaker (HVDCCB) test bench that differs significantly from conventional test benches. The proposed test bench consists of a modular multilevel cascaded converter (MMCC) that is based on H-bridge cells, an output inductor, and an auxiliary capacitor bank. The proposed test bench is capable of generating controllable output currents up to several kiloamperes and output voltages up to several hundred kilovolts because each MMCC cell is operated by phase-shifted pulse-width-modulated (PSPWM) signals. Consequently, the proposed test bench can simulate a wide range of fault conditions within hardware limitations to test different HVDCCB types with various current and voltage ratings. The flexibility of the proposed test bench is complemented by a longer service lifetime with inherent circuit protection in the case of operational failure of the HVDCCB. The concept of the proposed test bench is verified experimentally on a downscaled test bench that consists of nine H-bridge cells and operates at an equivalent switching frequency of 92:5 kHz.

关键词： DC circuit breaker HVDC MMCC test bench test circuit

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Partial Discharge Measurement at High Voltage test circuit having Static Frequency Converters

Partial Discharge Measurement at High Voltage Test Circuit h...

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IEEE International Power Modulator and High Voltage Conference (IPMHVC)

作者： Haller, Rainer Martinek, Petr Univ W Bohemia Prague Czech Republic

ISBN: (纸本)9781479940479;9781467373234

For testing of high voltage (h.v.) components under so-called unconventional frequency test conditions as h.v.- test source very often static frequency converters (SFC) were applied. A typical example for that is the testing of power transformers at higher frequency. In the past this test was provided by standardized motor-generator sets, but more and more alternative power sources having SFC-units are used. In that case the performing of sensitive diagnostic test procedure like partial discharge (pd) measurement seems to be impossible caused by vast electromagnetic disturbances which are generated by the switching part of the SFC. On the other hand the performing of such sensitive diagnostic measurement is obligatory. For overcoming of these problems two possibilities will be described in the paper. At first the EMI pulses which are coupled into the test circuit must be suppressed. Unfortunately, because of the mostly unknown "current-way" of these disturbances, the optimal solution of suppression must be found by a "half-empirical" way, taking into account the well-known EMC requirements. In addition to that the right choice of the commonly used filter located after the SFC-component is very important and should be designed following the performed EMC measures. For an exemplary h.v. test circuit the appropriate measures to minimize the EMI disturbances are described, at which a pd-sensitivity of similar to 30 pC could be obtained at the full range operation of SFC. For further increasing of pd-sensitivity additional measuring methods were investigated. For a desirable measuring sensitivity of similar to 10 pC the suppression of EMI signals, reached by additional measures should have at least a value of similar to 10 (20 dB), what could be obtained either by digital or by analogous methods. Using all the described measures for h.v. test circuits having SFC a pd measuring sensitivity in the range of few pC seems to be reachable.

关键词： test circuit Partial discharge measurement resting frequency high-voltage testing Electromagnetic interference European Monetary Institute Frequency converters Converters Discharge measurement ELECTRIC TRANSFORMERS additional measures Electric Power Source

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test circuits for HVDC circuit Breakers

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IEEE TRANSACTIONS ON POWER DELIVERY 2017年第1期32卷 285-293页

作者： Belda, N. A. Smeets, R. P. P. DNV GL KEMA Labs NL-6812 AR Arnhem Netherlands

High voltage direct current circuit breakers (HVDC CBs) are necessary for reliable and safe operation of future multiterminal meshed HVDC grids. So far no commercially mature products of such equipment exist. A few industrial concepts as a result of advances in power electronics have been proposed and prototypes have been built. However, performances of these concepts have never been demonstrated under realistic operation conditions. Since these tests require construction of high power DC sources incurring significant investment costs, alternative test circuits providing equivalent stresses must be considered. In this paper various test methods and circuits used for testing HVDC CBs are investigated and their performance is evaluated against the stresses in a conceptual future HVDC grid. A novelmethod of testing an HVDC CB using existing installations in a high power ac test laboratory is proposed and its prospective fault current and voltage is experimentally demonstrated. It is concluded that adequate test circuits need to maintain the supply voltage not only up to the current zero in the main interrupter unit of the HVDC CB, but also during the entire energy dissipation phase of the interruption process.

关键词： HVDC circuit breaker power system transients PSCAD test circuit test facilities testing

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Performance Demonstration of HVDC circuit Breakers 6

Performance Demonstration of HVDC Circuit Breakers

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6th International Conference on Electric Power Equipment - Switching Technology (ICEPE-ST)

作者： Belda, Nadew Adisu Smeets, Rene Peter Paul Plet, Cornelis Arie KEMA Labs Labs Dev Innovat Arnhem Netherlands DNV Energy Syst Canada Inc Renewables Advisory Toronto ON Canada

ISBN: (纸本)9781665448673

This paper provides an overview of the complete research and development track that led to the public demonstration of three HVDC circuit breaker (CB) technologies rated up to 350 kV, 20 kA. The lessons learned are used as inputs to the international standardization activities related with the testing of HVDC CBs. Since HVDC grids are almost completely non-existent, a model of a conceptual HVDC grid is used to study the impact of faults on such grids. By embedding realistic models of HVDC CBs, this study is used to quantify the electrical stresses to which the HVDC CBs are subjected. Next, a detailed set of test requirements is set up, consisting of clearly defined test-duties, to qualify the breaker for its main task - fault current interruption under full power condition. These test requirements are agreed among the manufacturers of the three technologies of HVDC CBs. In addition, a study evaluating the practical aspects as well as comparing the performance of possible test circuits singled out the test circuit based on low-frequency AC shortcircuit generators as technically the best option to replicate the stresses as in service, quantified by a number of essential phases in the interruption process.

关键词： Demonstration HVDC circuit Breaker PROMOTioN test circuit testing

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A test circuit for Extremely Low Gate Leakage Current Measurement of 10 aA for 80 000 MOSFETs in 80 s

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IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING 2013年第3期26卷 288-295页

作者： Inatsuka, Takuya Kumagai, Yuki Kuroda, Rihito Teramoto, Akinobu Suwa, Tomoyuki Sugawa, Shigetoshi Ohmi, Tadahiro Tohoku Univ Grad Sch Engn Sendai Miyagi 9808579 Japan LAPIS Semicond Miyagi Co Ltd Ohira Miyagi 9813693 Japan Tohoku Univ New Ind Creat Hatchery Ctr Sendai Miyagi 9808579 Japan

We discuss the measurement accuracy of the test circuit, which can evaluate statistical characteristics of gate leakage current of small area metal-oxide-semiconductor field-effect transistors (MOSFETs) in a very short time. The accuracy and precision of the gate leakage current obtained by the test circuit are verified for a wide range. As a result it is confirmed that very accurate gate current of 10(-17) A +/- 10% is able to be measured with this method. Using this test circuit, we can evaluate the gate leakage current at a wide electric field range, which is important in discussing the conduction mechanism of gate leakage current.

关键词： Electrical stress gate leakage current low current measurement MOSFET statistical evaluation test circuit

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A CAD approach for suppression of power supply noise and performance analysis of some multi-core processors in pre-layout stage

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MICROSYSTEM TECHNOLOGIES-MICRO-AND NANOSYSTEMS-INFORMATION STORAGE AND PROCESSING SYSTEMS 2019年第5期25卷 1977-1986页

作者： Mitra, Partha Bhaumik, Jaydeb SDET Brainware Grp Inst Dept Elect & Commun Engn Kolkata 700124 India Haldia Inst Technol Dept Elect & Commun Engn Haldia 721657 India

In modern system-on-chip, the number of transistors has grown exponentially. This requires an efficient electrical power distribution network for proper functioning of the chip. Voltages at different nodes with respect to the desired level may vary which correspond to generation of supply noise. This paper deals with the estimation and allocation of decoupling capacitance for reduction of supply noise at the pre-layout level. Usually, decoupling capacitors are placed near the noisy functional modules, which acts as local charge storing devices and effectively reduce the transients. In this work, analysis of various sources of supply noises has been performed. Depending on the amount of supply noise, the decoupling capacitance has been estimated and allocated with minimum increment in power consumption and propagation delay. We have considered 512-points, 1-k point, 2-k point and 4-k point Fast Fourier Transform processors and International test Conference 1999 (b14 and b17) benchmark circuits as our test circuits. This work reports up to 51.9% reduction of peak supply noise at the cost of 0.48 and 1.44% increase in power consumption and delay respectively. This estimation and subsequent allocation of decoupling capacitances will help for more accurate design and implementation at the layout stage.

关键词： Multi-core processors task analysis capacitance DECOUPLING test circuit decoupling capacitor Power consumption Electric Power Source

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