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Architecture and Evaluation of an Asynchronous array of Simple processors

JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2008年第3期53卷 243-259页

作者： Yu, Zhiyi Meeuwsen, Michael J. Apperson, Ryan W. Sattari, Omar Lai, Michael A. Webb, Jeremy W. Work, Eric W. Mohsenin, Tinoosh Baas, Bevan M. Univ Calif Davis ECE Dept Davis CA 95616 USA

This paper presents the architecture of an asynchronous array of simple processors (AsAP), and evaluates its key architectural features as well as its performance and energy efficiency. The AsAP processor calculates DSP applications with high energy-efficiency, is capable of high-performance, is easily scalable, and is well-suited to future fabrication technologies. It is composed of a two-dimensional array of simple single-issue programmable processors interconnected by a reconfigurable mesh network. processors are designed to capture the kernels of many DSP algorithms with very little additional overhead. Each processor contains its own tunable and haltable clock oscillator, and processors operate completely asynchronously with respect to each other in a globally asynchronous locally synchronous (GALS) fashion. A 6x6 AsAP array has been designed and fabricated in a 0.18 mu m CMOS technology. Each processor occupies 0.66 mm(2), is fully functional at a clock rate of 520-540 MHz at 1.8 V, and dissipates an average of 35 mW per processor at 520 MHz under typical conditions while executing applications such as a JPEG encoder core and a complete IEEE 802.11a/g wireless LAN baseband transmitter. Most processors operate at over 600 MHz at 2.0 V. processors dissipate 2.4 mW at 116 MHz and 0.9 V. A single AsAP processor occupies 4% or less area than a single processing element in other multi-processor chips. Compared to several RISC processors (single issue MIPS and ARM), AsAP achieves performance 27-275 times greater, energy efficiency 96-215 times greater, while using far less area. Compared to the TI C62x high-end DSP processor, AsAP achieves performance 0.8-9.6 times greater, energy efficiency 10-75 times greater, with an area 7-19 times smaller. Compared to ASIC implementations, AsAP achieves performance within a factor of 2-5, energy efficiency within a factor of 3-50, with area within a factor of 2.5-3. These data are for varying numbers of AsAP processors per bench

关键词： array processor chip multi-processor digital signal processing DSP globally asynchronous locally synchronous GALS many-core multi-core programmable DSP

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An FPGA array for cellular genetic algorithms: Application to the minimum energy broadcast problem

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MICROprocessorS AND MICROSYSTEMS 2018年 58卷 1-12页

作者： dos Santos, Pedro Vieira Alves, Jose Carlos Ferreira, Joao Canas Univ Porto INESC TEC INESC Technol & Sci Porto Portugal Univ Porto FEUP Fac Engn Porto Portugal

The genetic algorithm is a general purpose optimization metaheuristic for solving complex optimization problems. Because the algorithm usually requires a large number of iterations to evolve a population of solutions to good final solutions, it normally exhibits long execution times, especially if running on low-performance conventional processors. In this work, we present a scalable computing array to parallelize and accelerate the execution of cellular GAs (cGAs). This is a variant of genetic algorithms which can conveniently exploit the coarse-grain parallelism afforded by custom parallel processing. The proposed architecture targets Xilinx FPGAs and was implemented as an auxiliary processor of an embedded soft-core CPU (MicroBlaze). To facilitate the customization for different optimization problems, a high-level synthesis design flow is proposed where the problem-dependent operations are specified in C++ and synthesised to custom hardware, thus demanding of the programmer only minimal knowledge of low-level digital design for FPGAs. To demonstrate the efficiency of the array processor architecture and the effectiveness of the design methodology, the development of a hardware solver for the minimum energy broadcast problem in wireless ad hoc networks is employed as a use case. Implementation results for a Virtex-6 FPGA show significant speedups, especially when comparing to embedded processors used in current FPGA devices.

关键词： Genetic algorithms FPGA array processor High-level synthesis

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MEMORY SYSTEMS FOR IMAGE-PROCESSING

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IEEE TRANSACTIONS ON COMPUTERS 1978年第2期27卷 113-125页

作者： VANVOORHIS, DC MORRIN, TH IBM

An image can be represented by a two-dimensional array of "image points," which are sets of integers that each describe the color and intensity of a portion of the image. Image-processing operations require that an image or partial image be stored in a memory system that permits access to sequences of image points along any row or column of this image array and/or to the image points within small rectangular areas of the array. This paper describes a number of memory systems that permit access to 1 × pq,pq × 1 and/or p × q subarrays of an image array, where p and q are design parameters.

关键词： array processor array storage image processing memory system parallel memory parallel processor

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REMARC: Reconfigurable multimedia array coprocessor

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IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS 1999年第2期E82D卷 389-397页

作者： Miyamori, T Olukotun, K Toshiba Corp Kawasaki Kanagawa 2108520 Japan Stanford Univ Fac Elect Engn Stanford CA 94305 USA

This paper describes a new reconfigurable processor architecture called REMARC (Reconfigurable Multimedia array Coprocessor). REMARC is a small array processor that is tightly coupled to a main RISC processor. It consists of a global control unit and 64 16-bit processors called nano processors. REMARC is designed to accelerate multimedia applications, such as video compression, decompression, and image processing. These applications typically use 8-bit or 16-bit data therefore, each nano processor has a 16-bit datapath that is much wider than those of other reconfigurable coprocessors. We have developed a programming environment for REMARC and several realistic application programs, DES encryption, MPEG-2 decoding, and MPEG-2 encoding. REMARC can implement various parallel algorithms which appear in these multimedia applications. For instance, REMARC can implement SIMD type instructions similar to multimedia instruction extensions for motion compensation of the MPEG-2 decoding. Furthermore, the highly pipelined algorithms, like systolic algorithms, which appear in motion estimation of the MPEG-2 encoding can also be implemented efficiently. REMARC achieves speedups ranging from a factor of 2.3 to 21.2 over the base processor which is a single issue processor or a-issue superscalar processor. We also compare its performance with multimedia instruction extensions. Using more processing resources, REMARC can achieve higher performance than multimedia instruction extensions.

关键词： computer architecture reconfigurable computer array processor multimedia application

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SELECTING A processor FOR COMPUTATIONS IN MOLECULAR BIOPHYSICS

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COMPUTERS IN BIOLOGY AND MEDICINE 1988年第5期18卷 341-349页

作者： BOURNE, PE HENDRICKSON, WA Howard Hughes Medical Institute Department of Biochemistry and Molecular Biophysics Columbia University New York NY 10032.

A number of relatively low-cost processors are now available which employ architectural features previously found only on very expensive supercomputers. The speed of these computers makes it possible to reduce the time to solution of certain problems and to resolve large problems that previously were too time consuming to perform locally. A brief overview of this type of processor is given and the implications for computations in molecular biophysics are discussed in reference to the results of a benchmark that uses the refinement of a protein structure from X-ray crystallographic data.

关键词： Vector processor Benchmark Protein refinement array processor Molecular biophysics Parallel processors Multiple processors PROLSQ PROTIN

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ARCHITECTURAL SYNTHESIS OF LARGE, NEARLY REGULAR ALGORITHMS - DESIGN TRAJECTORY AND ENVIRONMENT

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ANNALES DES TELECOMMUNICATIONS-ANNALS OF TELECOMMUNICATIONS 1991年第1-2期46卷 49-59页

作者： DEWILDE, P DEPRETTERE, E DELFT UNIV TECHNOL DEPT ELECT ENGN2628 CD DELFTNETHERLANDS

We address the question of mapping a large, nearly regular numerical algorithm on an architecture of parallel processors whose extent in space is fixed - a fixed size array. The method that we present is generic in the sense that the mapping procedure is independent of the size of the original problem but adapts itself to the limited processing memory resources of the target array. The size of the original problem enters only as a parameter. The method is implemented as a set of tools of our HiFi design system which may truly be called an ''architecture compiler''. We give a description of the system and show examples as we go along.

关键词： ALGORITHM SIGNAL PROCESSING PARALLEL PROCESSING MULTIprocessor COMPUTER AIDED DESIGN array processor COMPUTER ARCHITECTURE

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COMPLETE BINARY SPANNING-TREES OF THE 8 NEAREST NEIGHBOR array

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IEEE TRANSACTIONS ON COMPUTERS 1985年第6期34卷 547-549页

作者： CHUGHTAI, MA Department of Electrical Engineering and Electronics University of Manchester Institute of Science & Technology Manchester England University of Engineering and Technology Lahore Pakistan. Abstract Authors References Cited By Keywords Metrics Similar Download Citation Email Print Request Permissions

Complete binary spanning trees of an n x n array of processors with an eight nearest neighbor interconnection pattern exist for a limited value of n. These spanning trees provide a fast route to accumulate information from all processors of the array, and allow certain problems to be solved as efficiently on an eight-neighbor array as on a tree-structured array. The condition under which complete binary spanning trees of a square array may exist is determined. This condition shows that complete binary spanning trees of an n x n eight-neighbor array exist only for n ≪ = 13. It is also observed that for n ≪ = 6, leaf nodes of these spanning trees lie on the periphery of the array.

关键词： array processor complete binary tree eight nearest neighbor array spanning tree

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PARALLEL PROCESSING SYSTEMS - A NOMENCLATURE BASED ON THEIR CHARACTERISTICS

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IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES 1987年第3期134卷 143-147页

作者： BASU, A Computer Science Unit Indian Statistical Institute Calcutta India

The paper presents a taxonomy for parallel processing systems. Because of technological limitations, high-speed computing has to be achieved nowadays by innovative architectures whose distinctive features cannot be clearly brought out by any of the taxonomies proposed to date. The paper discusses the drawbacks of these taxonomies before proposing a new method of classification based on some dominant architectural features, such as the level of concurrency, method of algorithm realisation, execution characteristic and control structure. The principal aim of proposing a new taxonomy is to develop a nomenclature which can be used to describe the salient features of all the types of parallel processing systems that have been proposed to date. In the last part of the paper it is shown how the nomenclature suggested in the proposed scheme of classification can be used to describe the ‘pure’ high-speed computing systems such as systolic array, pipeline processor, multiprocessor, data-flow processor, multifunction processor, array processor, associative processor and also the systems formed by hybridation of these ‘pure’ systems.

关键词： level of concurrency Computer architecture taxonomies systolic array array processor control structure high-speed computing multifunction processor pipeline processor multiprocessor Multiprocessing systems execution characteristic data-flow processor nomenclature parallel architectures associative processor parallel processing systems classification architectural features

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A Novel Architecture for Block Interleaving Algorithm in MB-OFDM Using Mixed Radix System

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2010年第6期18卷 1020-1024页

作者： Han, Youngsun Harliman, Peter Kim, Seon Wook Kim, Jong-Kook Kim, Chulwoo Korea Univ Sch Elect Engn Seoul 136701 South Korea

In this paper, we present a novel architecture of a block interleaver inMB-OFDM systems based on Mixed Radix System (MRS). We prove mathematically that the proposed architecture can support bit permutations in the interleaving process. The hierarchical property of our proposed MRS-based design methodology allows the proposed architecture to support all the required data rates in the MB-OFDM systems with simple modular design. Furthermore, the same design to be used for the interleaver can also be used for the operation of de-interleaving, which reduces the implementation complexity significantly. The latency of our architecture is as low as 6 MB-OFDM symbols. In addition, when comparing our proposed architecture with the conventional approach, we are able to reduce the implementation complexity by 85.5%, 69.4%, and 40.3% for 80, 200, and 480 Mb/s data rates, respectively, while improving our operating maximum clock frequency by more than 3.3 times over the conventional design. We also show that the power consumption is reduced by 87.4%, 73.6%, and 39.8% for 80, 200, and 480 Mb/s, respectively.

关键词： array processor block interleaving MB-OFDM Mixed Radix System (MRS)

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Pixel sensor integrated neuromorphic VLSI system for real-time applications

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NEUROCOMPUTING 2008年第1-3期72卷 293-301页

作者： Karahaliloglu, Koray Gans, Patrick Schemm, Nathan Balkir, Sina Virginia Commonwealth Univ Dept Elect & Comp Engn Richmond VA 23284 USA Univ Nebraska Dept Elect Engn Lincoln NE 68588 USA

A pixel sensor integrated VLSI system, based on a bio-inspired neuromorphic model, is reported. The design employs photodiode sensors where the analog input states in related 2D cell array are programmed directly with visual patterns. The system functionality and specific image processing tasks are demonstrated with measurements, where real-time input patterns are introduced. The static power consumption estimations for the array are given, as larger arrays are feasible due to compact design. The estimated and measured numerical results are compared. The obtained convenient sensor integration can lead to real-time high-resolution applications of this system. (C) 2008 Elsevier B.V. All rights reserved.

关键词： array processor CMOS Reaction-diffusion Fitzhugh-Nagumo CNN

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