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IEEE International Young Scientists Forum on Applied Physics and Engineering (YSF)

作者： Yershov, Roman D. Yakosenko, Denys S. Yatsenko, Serhii I. CNUT Ind Elect Dept Chernihiv Ukraine

ISBN: (纸本)9781538629949

The problem of scalable and optimal behavior style description of the binary encoder implementation into FPGA was examined. The structural synthesis technique of the binary encoder with input requests filtration and error detection circuits, which allow improving FPGA resource utilization in comparison with typical description, was proposed. The results of research and development, which have presented by relationship equations for encoder and its structure generation algorithm, were confirmed by correct register-transfer level representation and during timing simulation. The numeric comparative assessments of FPGA recourses utilizing depending both the encoder inputs number and FPGA ICs family from different vendor was implemented.

关键词： binary encoder VHDL FPGA structural synthesis regular structure scalable design

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Terahertz binary coder based on graphene metasurface

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CARBON 2021年 184卷 167-176页

作者： Gong, Yumin Hu, Fangrong Jiang, Mingzhu Zhang, Longhui Zou, Yingchang Jiang, Guobao Liu, Yongchen Guilin Univ Elect Technol Guangxi Key Lab Automat Detecting Technol & Instr Guilin 541004 Peoples R China Changsha Univ Coll Elect Informat & Elect Engn Hunan Engn Technol Res Ctr Optoelect Hlth Detect Changsha 410022 Peoples R China

In this paper, we demonstrate a terahertz (THz) binary encoder based on graphene metasurface. The unit cell of the device consists of two parallel metal bars and two split-ring resonators (SRRs) embedded with two graphene ribbons. For two SRRs in the unit cell, one is connected to an electrode on the right side, and the other is connected to the electrode on the left side of the device, respectively. When no voltage is applied, the device has two passbands whose central frequencies locating at 0.85 THz and 1.14 THz, respectively. Unlike many THz tunable filters which modulate the amplitude of different bands at the same time, this encoder can achieve separately modulation of each passband. By electrically adjusting the Fermi energy of graphene on each SRR individually, the maximum modulation depth at the two central frequencies can be up to 80% and 87%, respectively. Furthermore, the function of THz frequency range binary coding is realized, i.e., four different binary coders of 11, 10, 01 and 00 are obtained in the transmission. Our work paves a new way for the development of multifunctional integrated THz devices, which will be of great significance in THz switching, communication and one-chip integrated THz system. (c) 2021 Elsevier Ltd. All rights reserved.

关键词： Terahertz (THz) Graphene metasurface binary encoder Amplitude modulation

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Methodology and comparative design of an efficient 4-bit encoder with bubble error corrector for 1-GSPS flash type ADC

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IET CIRCUITS DEVICES & SYSTEMS 2020年第5期14卷 629-639页

作者： Hussain, Sarfraz Kumar, Rajesh Trivedi, Gaurav NERIST Dept Elect & Commun Engn Nirjuli 791109 Arunachal Prade India IIT Guwahati Dept Elect & Elect Engn Gauhati 781039 Assam India

The design of a 4-bit encoder with a bubble error correction of first order is described in this study. Since encoder restricts speed of the flash analogue-to-digital converter (ADC), therefore, an improved and faster encoder is an essential requirement to push its limits. encoder is divided into two parts: one-hot code generator [or bubble error corrector (BEC)] and binary encoder. binary encoder proposed in this study is the modified Fat-Tree encoder of types I and II. Three types of BECs which have been compared in this study are OR gate based, NAND gate based and the proposed BEC. The proposed BEC consumes less power and provides better speed as compared to NAND based and OR gate based BECs. It can be further employed for higher order bubble correction as well. The proposed BEC consumes dynamic power of 87.071 mu W and leakage power of 18.3563 pW exhibiting the delay of 38.3 ps with 1.8 V supply voltage and 1 GHz clock frequency. It has a power-delay product of 3.335 fJ, energy-delay product of 127.7305 Js and an intrinsic area of 4.753 mm(2).

关键词： encoding analogue-digital conversion error correction binary codes tree codes logic design higher order bubble correction BEC 4-bit encoder bubble error corrector 1-GSPS flash type ADC bubble error correction flash analogue-to-digital converter binary encoder Fat-Tree encoder NAND gate OR gate power 18 3563 pW voltage 1 8 V energy 3 335 fJ power 87 071 muW

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Design and simulation of a universal N-bit binary encoder using single electron linear threshold gates

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MICROELECTRONICS JOURNAL 2012年第3期43卷 205-215页

作者： Rehan, Sameh Ebrahim Mansoura Univ Commun & Elect Engn Dept Mansoura 35516 Egypt

The Single-Electron (SE) Linear Threshold Gate (LTG) is one of the basic functional Single-Electron Nano-Devices (SENDs). In this paper, using a SE LTG as the basic building block in an artificial neural network (ANN) is reviewed. A universal SE ANN 2-bit (4-to-2) binary encoder, which is composed of only two SE LTGs, is designed. The detailed schematic diagrams along with the corresponding SIMON 2 simulation results (that include input and output signals as well as the stability diagrams) of the designed binary encoder are included. The proposed SE ANN 2-bit binary encoder can easily be generalized to design n-bit binary encoders. As an example of this generalization, a SE ANN 3-bit (8-to-3) binary encoder, which is composed of three SE LTGs, is designed and its SIMON 2 simulation results are presented. This design is compared with the previously reported C-SET 3-bit binary encoder. (C) 2011 Elsevier Ltd. All rights reserved.

关键词： Single-electron nano-devices (SENDs) Tunnel junction (TJ) Linear threshold gate (LTG) binary encoder Artificial neural network (ANN) Stability plots

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Comparative Analysis of Low Power Novel encoders for Flash ADC in 45nm Technology 3

Comparative Analysis of Low Power Novel Encoders for Flash A...

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International Conference on Smart Technologies and Management for Computing, Communication, Controls, Energy and Materials (ICSTM)

作者： Kar, Aditi Das, Moushumi Nath, Bipasha Sarkar, Durba Majumder, Alak Tripura Inst Technol Dept ETCE Agartala India NIT Arunachal Pradesh Dept ECE Yupia India

ISBN: (纸本)9781479998555

The electronics world is faced with various challenges when attempting to integrate analog signals with discrete or digital systems. The ADC is not a new concept b y any means, but is still a topic of interest when it comes to technology due to its inevitable necessity in many systems being used today. Power consumption in ICs was always a challenging issue. Most of the technology emphasizes on speed, accuracy, less power consumption. In almost all digital functioning, encoders are mandatory. Decreasing power consumption in an encoder is an area of strong desire. In this paper, we have designed two novel ultra low power encoders for Flash ADC application and also show its comparison with previous encoder available in literature. The work has been done on Tanner tool v15 in 45 nm technology with various DC voltage supplies.

关键词： encoder Fat tree encoder Gray encoder binary encoder

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Crossover Structures for Logical Computations in Excitable Chemical Medium

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INTERNATIONAL JOURNAL OF UNCONVENTIONAL COMPUTING 2015年第2期11卷 165-184页

作者： Sun, Ming-Zhu Zhao, Xin Nankai Univ Inst Robot & Automat Informat Syst Tianjin Key Lab Intelligent Robot Tianjin 300071 Peoples R China Chinese Acad Sci Shenyang Inst Automat State Key Lab Robot Shenyang 110016 Peoples R China

It is known that spatially distributed excitable chemical medium is capable of performing chemical computation. As a kind of unconventional computation, chemical computation should have the ability to replicate basic functions in conventional computation, such as logic circuits. Owing to the planar structure of the excitable medium, it is difficult to implement crossing wires in excitable medium, which is very common in digital electronics. The chemical implementation of the crossover attracts more and more attention in these years. This paper concentrates on the design and realization of crossover in excitable medium, and discusses its applications in logical computations. Three kinds of combinational logic circuits, including binary adder, binary encoder and binary decoder are constructed. The simulation results demonstrate the effectiveness of crossover structures, as well as all the combinational logical devices.

关键词： Bclousov-Zhabotinsky reaction chemical computation excitable media crossover structure logic circuits binary adder binary encoder binary decoder

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A fast improved fat tree encoder for wave union TDC in an FPGA

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Chinese Physics C 2013年第10期37卷 56-62页

作者：沈奇赵雷刘树彬廖胜凯祁宾祥胡雪野彭承志安琪 State Key Laboratory of Particle Detection and Electronics University of Science and Technology of China Department of Modern Physics University of Science and Technology of China Hefei National Laboratory for Physical Sciences at Microscale

Up to now, the wave union method can achieve the best timing performance in FPGA-based TDC designs. However, it should be guaranteed in such a structure that the non-thermometer code to binary code （NTH2B） encoding process should be finished within just one system clock cycle. So the implementation of the NTH2B encoder is quite challenging considering the high speed requirement. Besides, the high resolution wave union TDC also demands that the encoder convert an ultra-wide input code to a binary code. We present a fast improved fat tree encoder （IFTE） to fulfill such requirements, in which bubble error suppression is also integrated. With this encoder scheme, a wave union TDC with 7.7 ps RMS and 3.8 ps effective bin size was implemented in an FPGA from Xilinx Virtex 5 family. An encoding time of 8.33 ns was achieved for a 276-bit non-thermometer code to a 9-bit binary code conversion. We conducted a series of tests on the oscillating period of the wave union launcher, as well as the overall performance of the TDC; test results indicate that the IFTE works well. In fact, in the implementation of this encoder, no manual routing or special constraints were required; therefore, this IFTE structure could also be further applied in other delay-chain-based FPGA TDCs.

关键词： wave union TDC FPGA binary encoder time interpolation

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ON THE QAM PARALLEL TURBO-TCM SCHEMES USING RECURSIVE CONVOLUTIONAL GF(2N) encoderS

ON THE QAM PARALLEL TURBO-TCM SCHEMES USING RECURSIVE CONVOL...

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European Signal Processing Conference

作者： Adrian Florin Paun Calin Vladeanu Ion Marghescu Safwan El Assad Alexandru Martian Telecommunications Department University Politehnica of Bucharest IREENA Ecole Polytechnique de l'Universite de Nantes

In this paper, parallel turbo quadrature amplitude modulation - trellis coded modulation (Turbo QAM-TCM) schemes are designed using recursive convolutional encoders over Galois field GF(2N). These encoders are designed using the nonlinear left-circulate (LCIRC) function. The LCIRC function performs a bit left circulation over the representation word. An optimum 1-delay GF(2N) recursive convolutional encoder scheme using LCIRC (RC-LCIRC) is proposed for QAM-TCM schemes. The minimum Euclidian distance is estimated for these QAM-TCM schemes and it is shown that these structures offer the maximum coding gains. However, the RC-LCIRC encoders are less complex than the corresponding binary encoders are. The optimum RC-LCIRC encoder is used as component encoder of a parallel turbo QAM-TCM transmission scheme, using the iterative multilevel log-MAP algorithm in the receiver. The bit error rate (BER) is estimated by simulation for the proposed Turbo QAM-TCM transmissions over an additive white Gaussian noise (AWGN) channel, and the results are similar to the conventional Turbo-TCM schemes.

关键词： encoder Turbo Worm gears Quadrature amplitude modulation Bit error rate Scheme AWGN binary encoder

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