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bit-parallel Algorithms for Exact Circular String Matching

COMPUTER JOURNAL 2014年第5期57卷 731-743页

作者： Chen, Kuei-Hao Huang, Guan-Shieng Lee, Richard Chia-Tung Natl Chi Nan Univ Dept Comp Sci & Informat Engn Nantou Taiwan

In this paper, we deal with the exact circular string matching problem (abbreviated as ECSM). Given a string P = p(1) p(2) a <- p(m), a string P-(i) = p(i) p(i+1) a <- p(m) p(1) a <- p(i-1), for 1 a parts per thousand currency sign i a parts per thousand currency sign m, is a circular string of P. Given a text string T = t(1)t(2) a <- t(n) and a pattern P, the ECSM problem is to find all occurrences of P-(i) in text T for 1 a parts per thousand currency sign i a parts per thousand currency sign m. This paper proposes two algorithms that perform searching of a circular string on text using the bit-parallel technique. Our algorithms use only the composition of bitwise-logical operations and basic arithmetic operations, and apply this technique to solve the problem. These algorithms are given names CSBNDM and CSBNDNq, respectively. We give several experiments to verify that they have good performance for random strings and DNA sequences.

关键词： circular string matching exact string matching bit-parallel processing

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Word-parallel CRC computation on VLIW DSP

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ELECTRONICS LETTERS 2002年第2期38卷 64-65页

作者： Hubaux, D Legat, JD Univ Catholique Louvain Microelect Lab DICE B-1348 Louvain Belgium

Cyclic redundancy check (CRC) is widely used for error detection. For optimal performances a method has been developed for bit-parallel processing, but it may not take advantage of parallel processor architecture. Here, a method is proposed for using. the toll power of a very long instruction word (VLIW) digital signal processor (DSP) architecture in CRC computation. The method to at least four times faster for 8, 16 and 32 bits CRC.

关键词： word-parallel algorithm Digital signal processing chips Microprocessors and microcomputers 32 bit digital signal processing chips error detection parallel processor architecture 16 bit optimal performance parallel architecture CRC computation Semiconductor integrated circuits bit-parallel processing parallel algorithms VLIW DSP architecture parallel architectures very long instruction word digital signal processor cyclic redundancy check word-parallel CRC computation 8 bit redundancy VLIW DSP

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Associative graph processor and its properties

Associative graph processor and its properties

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4th International Conference on parallel Computing in Electrical Engineering (PARELECT 2004)

作者： Nepomniaschaya, A Kokosinski, Z Inst Computat Math & Math Geophys Novosibirsk 90 Russia

ISBN: (纸本)0769520804

In this paper a model of a versatile associative graph processor called AGP is proposed. The model can work both in bit-serial and in bit-parallel mode and enables simultaneous search for a set of comparands and selection of the search types. In addition it has some built-in operations designed for associative graph algorithms. The selected functions and basic procedures of this model are described and its possible architecture is discussed.

关键词： associative parallel processor bit-parallel processing associative graph processing multiple-search

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FPGA implementations of a parallel associative processor with multi-comparand multi-search operations

FPGA implementations of a parallel associative processor wit...

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7th International Symposium on parallel and Distributed Computing

作者： Kokosinski, Zbigniew Malus, Bartlomiej Cracow Univ Technol Fac Elect & Comp Eng PL-31155 Krakow Poland

ISBN: (纸本)9780769534725

Multi-comparand associative processors are efficient in parallel processing of complex search problems that arise from many application areas including computational geometry, graph theory and list/matrix computations. In this paper we report new FPGA implementations of a multi-comparand multi-search associative processor The architecture of the processor working in a combined bit-serial/bit-parallel word-parallel mode and its functions arc, described. Then, several implementations of associative processors in VHDL, using Xilinx Foundation ISE software and Digilent development boards with Xilinx FPGA devices are reported. Parameters of the implemented FPGA processors are presented and discussed.

关键词： parallel associative processor SIMD FPGA processor bit-parallel processing multiple-search

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64-GHz Datapath Demonstration for bit-parallel SFQ Microprocessors Based on a Gate-Level-Pipeline Structure

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IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY 2021年第5期31卷

作者： Kashima, Ryota Nagaoka, Ikki Tanaka, Masamitsu Yamashita, Taro Fujimaki, Akira Nagoya Univ Dept Elect Chikusa Ku Furo Cho Nagoya Aichi 4648603 Japan

We successfully demonstrated an 8-bit-wide, bit-parallel datapath composed of an arithmetic logic unit and register files for high-throughput oriented SFQ microprocessors based on a gate-level-pipeline structure. Achieving high-speed operation in the bit-parallel datapath is difficult because of feedback paths. We used concurrent-flow clocking and counter-flow clocking in combination to solve the timing problem at the feedback path in the datapath, and we optimized the number of JJs and pipeline stages in the register file for solving the timing issue. We designed the datapath with the cell library for the AIST 10 kA/cm(2) Advanced Process. The total number of pipeline stages, Josephson junctions, and circuit area of the designed datapath were 52, 18448, and 3.81 mm x 4.05 mm, respectively. We obtained a relatively wide bias margin of the designed datapath at the target clock frequency of 50 GHz, and it operated up to 64 GHz in on-chip high-speed testing.

关键词： Single flux quantum (SFQ) circuit bit-parallel processing gate-level-pipeline structure high throughput datapath

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Lowering Latency in a High-Speed Gate-Level-Pipelined Single Flux Quantum Datapath Using an Interleaved Register File

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IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY 2023年第5期33卷

作者： Kashima, Ryota Nagaoka, Ikki Nakano, Tomoki Tanaka, Masamitsu Yamashita, Taro Fujimaki, Akira Nagoya Univ Dept Elect Nagoya 4648603 Japan Tohoku Univ Dept Appl Phys Sendai 9808577 Japan

In this paper, we successfully demonstrate the 50-GHz operation of a microprocessor datapath based on single-flux -quantum (SFQ) logic with a gate-level pipeline (GLP) structure. The microprocessor datapath features a register file (RF), an arithmetic logic unit (ALU), and a long feedback loop that connects these components. Interleaved data-processing is applied in the RF. As the operating frequency of the RF is half that of the ALU, the timing constraints are eased;thus, we can reduce the number of pipeline stages used for timing adjustments. We designed a 4-bit datapath using the proposed technique, targeting 50-GHz opera-tion. Compared to the conventional datapath, the total number of pipeline stages and the latency decreased from 49 to 24 and from 980 to 760 ps respectively. We fabricated test chips using the AIST Nb 9-layer 10-kA/cm(2) process, and performed successful on-chip high-speed tests. In addition, our preliminary experiments suggest that we can expect 1.6-fold higher throughput at an 80-GHz clock frequency, at the cost of a 10% increase in latency.

关键词： Radio frequency Clocks Pipelines Microprocessors Throughput Logic gates Delays bit-parallel processing gate-level-pipeline microprocessor single-flux-quantum logic

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