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Impact of Supply Voltage and Frequency on the Soft Error Rate of logic Circuits

IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2013年第6期60卷 4200-4206页

作者： Mahatme, N. N. Gaspard, N. J. Jagannathan, S. Loveless, T. D. Bhuva, B. L. Robinson, W. H. Massengill, L. W. Wen, S-J Wong, R. Vanderbilt Univ Dept Elect Engn & Comp Sci Nashville TN 37212 USA

Alpha particle irradiations of 28-nm combinational logic and flip-flop circuits under different supply voltage and frequency operating conditions are investigated. Results indicate that while the supply voltage has a strong impact on the alpha particle soft error rate of flip-flops, the combinational logic error rate is relatively unaffected by supply voltage variation. Simulations are used to explain the results and highlight the differences between low-LET alpha particle irradiation and heavy-ion irradiation as far as voltage dependence of the logic soft error rate is concerned. Moreover, frequency has a much stronger impact on the logic soft error rate as compared to the flip-flop soft error rate. As a result, the frequency at which soft errors from combinational logic circuits will exceed errors from flip-flops decreases as the voltage increases. The impact of these observations is discussed in the context of soft-error mitigation strategies.

关键词： combinational logic high frequency circuits soft error rate supply voltage variation

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Estimating the Frequency Threshold for logic Soft Errors

Estimating the Frequency Threshold for Logic Soft Errors

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IEEE International Reliability Physics Symposium (IRPS)

作者： Mahatme, N. N. Gaspard, N. J. Jagannathan, S. Loveless, T. D. Abdel-Aziz, H. Bhuva, B. L. Massengill, L. W. Wen, S. -J. Wong, R. Vanderbilt Univ Nashville TN 37212 USA Cisco Syst Inc San Jose CA USA

ISBN: (纸本)9781479901135;9781479901128

logic soft errors are expected to contribute significantly towards overall soft-error failure-in-time (FIT) rates in the GHz frequency range. In this paper, the contribution of logic soft-errors, to the total soft error rate of circuits at the 28-nm technology node at high frequencies are quantified. Results suggest that the alpha particle logic soft error contribution to chip-level soft error rate is almost 50% at 0.5 GHz. The frequency threshold at which logic soft errors could exceed flip-flop errors is identified for ISCAS benchmark circuits. For most of the circuits analyzed, the frequency threshold is in the 0.9-2 GHz range. This suggests that logic soft errors could be major problem along with flip-flop errors as circuits operate at higher frequencies.

关键词： combinational logic Soft errors frequency technology scaling

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Open-Loop Control of Hybrid Stepper Motor with Two Phases Using Voltage to Frequency Converter

Open-Loop Control of Hybrid Stepper Motor with Two Phases Us...

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8th International Symposium on Advanced Topics in Electrical Engineering (ATEE)

作者： Mihalache, George Zbant (Adam), Andreea Livint, Gheorghe Tech Univ Gheorghe Asachi Iasi Romania Iasi Romania

ISBN: (纸本)9781467359801;9781467359795

Positioning systems are powered by different types of electric motors. A special category of electric motors, which are increasingly used in systems, are hybrid stepper motors (the most common example are with two phases). Due the simplicity of construction, command and control, they are used even in other electric drive systems. This paper presents a new method of Matlab simulation of a controller driver for a hybrid stepper motor with full step sequence, using a voltage to frequency converter. The results of the simulation of the proposed control scheme are quite satisfactory.

关键词： full step combinational logic hybrid stepper motor

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Zero-Delay FPGA-Based Odd-Even Sorting Network

Zero-Delay FPGA-Based Odd-Even Sorting Network

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IEEE Symposium on Computers and Informatics (ISCI)

作者： Hematian, Amirshahram Chuprat, Suriayati Manaf, Azizah Abdul Parsazadeh, Nadia Univ Teknol Malaysia Adv Informat Sch Kuala Lumpur Malaysia

ISBN: (纸本)9781479902101

Sorting is one of the most well-known problems in computer science and is frequently used for benchmarking computer systems. It can contribute significantly to the overall execution time of a process in a computer system. Dedicated sorting architectures can be used to accelerate applications and/or to reduce energy consumption. In this paper, we propose an efficient sorting network aiming at accelerating the sorting operation in FPGA-based embedded systems. The proposed sorting network is implemented based on an Optimized Odd-even sorting method (O-2) using fully pipelined combinational logic architecture and ring shape processing. Consequently, (O-2) generates the sorted array of numbers in parallel when the input array of numbers is given, without any delay or lag. Unlike conventional sorting networks, (O-2) sorting network does not need memory to hold data and information about sorting, and neither need input clock to perform the sorting operations sequentially. We conclude that by using (O-2) in FPGA-based image processing, we can optimize the performance of filters such as median filter which demands high performance sorting operations for real-time applications.

关键词： combinational logic FPGA Odd-Even Sort Parallel Computing Pipeline Architecture Real-time Sorting Networks

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Comparison of Alpha-particle and Neutron-induced combinational and Sequential logic Error Rates at the 32nm Technology Node

Comparison of Alpha-particle and Neutron-induced Combination...

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47th Annual IEEE International Reliability Physics Symposium

作者： Gill, B. Seifert, N. Zia, V. Intel Corp Hillsboro OR 97124 USA

ISBN: (纸本)9781424428885

We report on particle induced upset rates of combinational and sequential logic. A novel test chip has been designed in a 32nm process to study the effects of single event transients (SET) and to verify the accuracy of our simulation models. The test chip has been tested under neutron and alpha particle radiation. Our measured data verify simulation-based projections that while static logic at the 32nm technology node is sensitive to both alpha particle and neutron radiation, it is not a dominant contributor at the chip-level.

关键词： Alpha particle combinational logic single event effects SEE SET single-event transient soft errors SE

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C-CREST Technique for combinational logic SET Testing

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2008年第6期55卷 3347-3351页

作者： Ahlbin, J. R. Black, J. D. Massengill, L. W. Amusan, O. A. Balasubramanian, A. Casey, M. C. Black, D. A. McCurdy, M. W. Reed, R. A. Bhuva, B. L. Vanderbilt Univ Inst Space & Def Elect Nashville TN 37235 USA Vanderbilt Univ Off Dean Sch Engn Nashville TN 37235 USA

SEUs due to combinational logic in 90 urn CMOS is analyzed at various-speeds using a new design approach called the combinational Circuit for Radiation Effects Self-Test (C-CREST). C-CREST allows the cross-section of combinational logic to be increased while minimizing propagation delay. The design was fabricated in IBM's 9SF CMOS process and underwent broadbeam testing that distinguished combinational logic errors from latch errors. Results confirm that the design is effective in testing combinational logic for SE vulnerabilities with minimum speed penalty.

关键词： combinational logic DICE latch single event single event transient single event upset window of vulnerability

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Open-Loop Control of Hybrid Stepper Motor with Two Phases Using Voltage to Frequency Converter

Open-Loop Control of Hybrid Stepper Motor with Two Phases Us...

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International Symposium on Advanced Topics in Electrical Engineering

作者： George Mihalache Andreea.Zbant (Adam) Gheorghe Livint Technical University "Gheorghe Asachi" of Iasi Romania

ISBN: (纸本)9781467359795

关键词： full step combinational logic hybrid stepper motor

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Expedited Response Compaction for Scan Power Reduction

Expedited Response Compaction for Scan Power Reduction

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29th IEEE VLSI Test Symposium (VTS)/Workshop on Design for Reliability and Variability (DRV)

作者： Saeed, Samah Mohamed Sinanoglu, Ozgur NYU Polytech Inst Dept Comp Sci New York NY 10003 USA New York Univ Comp Engn Dept Abhu Dhabi U Arab Emirates

ISBN: (纸本)9781612846552

Transitions embedded in between consecutive stimulus/response bits toggle scan cells during shift operations. The consequent switching activity in the scan chains further propagate into the combinational logic, resulting in elevated power dissipation levels, and thus, endangering the reliability of the chip being tested. Based on the observation that the content of scan chains during shift operations is irrelevant and unimportant, we propose an expedited response compaction technique in order to reduce power dissipation during scan operations. Parallelized (and expedited) compaction operations help compress the entire capture response onto a single reference chain during the first portion of shift cycles, enabling a simultaneous constant-0 feed to all the remaining chains, in which no scan-out power is dissipated during the subsequent shift cycles. This DfT-based approach is non-intrusive for design flow, requires a very minor investment in area, and in turn delivers significant savings in test power. The proposed solution reduces test power without resorting to x-filling, enabling orthogonal x-filling techniques to be applied in conjunction, while retaining the observed responses intact. Experimental results justify the efficacy of the proposed technique in attaining test power reductions.

关键词： Clocks Compaction Computer architecture DfT Feeds logic gates Power dissipation Rendering (computer graphics) boundary scan testing chip reliability combinational logic design for testability design for testability expedited response compaction logic design logic testing orthogonal x-filling techniques power dissipation scan chains scan power reduction

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Single-Event Transient Mitigation in Sub-micron combinational Circuits

Single-Event Transient Mitigation in Sub-micron Combinationa...

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54th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)

作者： Haghi, Mahta Draper, Jeff Univ Southern Calif Ming Hsieh Dept Elect Engn Los Angeles CA 90089 USA Univ Southern Calif Inst Informat Sci Marina Del Rey CA 90089 USA

ISBN: (纸本)9781612848570

In this paper we use a pair of cross-coupled inverters as a weak-latch to mitigate Single Event Transient (SET) effects in combinational logic for sub-micron technologies. A weak-latch is added to a sequential element input to slow down the data transitions and as a result filters out SET pulses that are faster than its delay. By applying this method we succeed to completely filter out transient pulse widths of up to 350 ps and to decrease SET pulse widths of up to 500 ps by more than 50%. SET pulse width measurements from 2-D TCAD simulations show that for 65-nm technology SET pulses induced by heavy ion particles with energies up to 14 ***(2)/mg can be completely filtered while SET pulses produced by particles with energies up to 20 ***(2)/mg are narrowed down by more than half of their original pulse width by using this weak-latch.

关键词： 2D TCAD simulations Clocks Filtering Latches logic gates MOS devices SET pulse width combinational circuits combinational logic cross-coupled inverters single-event transient mitigation size 65 nm submicron combinational circuits weak latch

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Impact of Synthesis Constraints on Error Propagation Probability of Digital Circuits

Impact of Synthesis Constraints on Error Propagation Probabi...

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IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

作者： Limbrick, Daniel B. Yue, Suge Robinson, William H. Bhuva, Bharat L. Vanderbilt Univ Dept Elect Engn & Comp Sci Nashville TN 37232 USA Bejing Microelect Technol Inst Beijing Peoples R China

ISBN: (纸本)9780769545561

Optimization algorithms for the synthesis of digital logic circuits have been used to automate the process of meeting design constraints like area and timing. These algorithms affect a circuit's topology and therefore its vulnerability to soft errors. This paper investigates the impact that these optimizations have on the error propagation probability of various circuit benchmarks. Results indicate that a decrease in delay and area corresponds with an increase in error propagation probability. Additionally, an increase in mapping effort corresponds to an increase in error propagation probability.

关键词： logic synthesis constraint optimization logical masking error propagation probability combinational logic soft error

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