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DCT/IDCT Constant Geometry Array Processor for Codec on Display Panel

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 2018年第4期18卷 403-422页

作者： You, Jaehee Hongik Univ Sch Elect & Elect Engn 72-1 Sangsudong Mapogu Seoul 12179 South Korea

Algorithms, architectures and 8 X 8 processing element chip design are discussed based on constant geometry 2-Dim. DCT and IDCT. Both DCT and IDCT can be computed with the same hardware for image codec applications. An array of identical PEs is used for butterfly as well as recursive addition stages only with programming of regular interconnections between stages for fault tolerance of system on panel or flexible display panel. Also methodologies to optimize computation speed and amount of required hardware are discussed. An efficient distributed arithmetic ROM for coefficient multiplication is proposed to minimize chip area and to facilitate the PE programming. Chip area, computation time, with image qualities are evaluated with advantages.

关键词： DCT IDCT system on panel constant geometry fault tolerance distributed arithmetic

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SPEED-OPTIMIZED MICROPROCESSOR IMPLEMENTATION OF A DIGITAL-FILTER

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IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES 1981年第3期128卷 85-93页

作者： TAN, BS HAWKINS, GJ Department of Electrical Engineering Imperial College of Science and Technology London UK

A practical, efficient scheme is described for the implementation of a real-time programmable digital filter using a microprocessor. The use of distributed arithmetic is known to be able to provide increased speeds by avoiding time-consuming multiplications. To achieve maximum speeds, the working program in a microprocessor implementation should, as far as possible, contain only those instructions which perform the arithmetic functions. High component efficiency is also achieved if the inherent control capabilities of the microprocessor are fully utilised, in particular where support hardware elements are used. Simple techniques are proposed for meeting the above objectives, which are inexpensive to implement and are readily adaptable for most standard microprocessors. The low cost and enhanced speed of implementation makes it attractive as an economical alternative to hard-wired digital filters for working frequencies in the audio and telephony range of frequencies and as a building block for cascade realisation of larger length filters, particularly of the FIR type. Some results of an experimental model using the commercial standard 8080A micropressor are given and comparisons with implementations for other micropressors are made.

关键词： optimisation distributed arithmetic speed optimised 8080A microprocessor Microprocessors and microcomputers Digital filters partitioning digital filters microprocessor chips programmable digital filter microprocessor implementation digital filter

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Accelerating colour space conversion on reconfigurable hardware

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IMAGE AND VISION COMPUTING 2005年第11期23卷 935-942页

作者： Bensaali, F Amira, A Queens Univ Belfast Sch Comp Sci Belfast BT7 1NN Antrim North Ireland

Colour space conversion is very important in many types of image processing applications including video compression. This operation consumes up to 40% of the entire processing power of a highly optimised decoder. Therefore, techniques which efficiently implement this conversion are desired. This paper presents two novel architectures for efficient implementation of a Colour Space Converter (CSC) suitable for Field Programmable Gate Array (FPGAs) and VLSI. The proposed architectures are based on distributed arithmetic (DA) ROM accumulator principles. The architectures have been implemented and verified using the Celoxica RC1000 FPGA development board. In addition, they are platform independent and have a low latency (eight cycles). The first architecture has a throughput of height, while the second one is fully pipelined and has a throughput of one and capable of sustained data rate of over 234 mega-conversions/s. (c) 2005 Elsevier B.V. All rights reserved.

关键词： colour space conversion field programmable gate array distributed arithmetic

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Power modeling and efficient FPGA implementation of FHT for signal processing

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2007年第3期15卷 286-295页

作者： Amira, Abbes Chandrasekaran, Shrutisagar Brunel Univ Dept Elect & Comp Engn Sch Engn & Design Uxbridge UB8 3PH Middx England

Fast Hadamard transform (FHT) belongs to the family of discrete orthogonal transforms and is used widely in image and signal processing applications. In this paper, a parameterizable and scalable architecture for FHT with time and area complexities of O(2(W + 1)) and O(2N(2)), respectively, has been proposed, where W and N are the word and vector lengths. A novel algorithmic transformation for the FHT based on sparse matrix factorization and distributed arithmetic (DA) principles has been presented. The architecture has been parallelized and pipelined in order to achieve high throughput rates. Efficient and optimized field-programmable gate array implementation of the proposed architecture that yield excellent performance metrics has been analyzed in detail. Additionally, a functional level power analysis and modeling methodology has been proposed to characterize the various power and energy metrics of the cores in terms of system parameters and design variables. The mathematical models that have been derived provide quick presilicon estimate of power and energy measures, allowing intelligent tradeoffs when incorporating the developed cores as subblocks in hardware-based image and video processing systems.

关键词： discrete orthogonal transforms (DOTs) distributed arithmetic fast Hadamard transform (FHT) field-programmable gate array (FPGA) power modeling sparse matrices

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EFFICIENT SERIAL PARALLEL INNER-PRODUCT COMPUTATION

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ELECTRONICS LETTERS 1986年第14期22卷 750-752页

作者： SMITH, SG Department of Electrical Engineering University of Edinburgh Edinburgh UK

A class of serial/parallel architectures for inner-product computation is described, based on carry-save accumulator arrays. In their basic form such arrays form carry-save multiply/adders. A simple modification of the coefficient feed allows flexible extension to short vector inner-product computation using distributed arithmetic. These modules may be cascaded to handle longer vectors, forming high-level VLSI digital signal processing subsystems.

关键词： serial/parallel architectures distributed arithmetic carry-save accumulator arrays Digital arithmetic methods digital arithmetic multiply/adders VLSI digital signal processing subsystems Digital signal processing carry logic inner-product computation computerised signal processing coefficient feed

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High performance hardware design of compressor adder in DA based FIR filters for hearing aids

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INTERNATIONAL JOURNAL OF SPEECH TECHNOLOGY 2020年第4期23卷 807-814页

作者： Rammohan, S. Radha Jayashri, N. Bivi, Mariyam Aysha Nayak, Chinmaya Kumar Niveditha, V. R. Dr MGR Educ & Res Inst Dept Comp Applicat Chennai Tamil Nadu India King Khalid Univ Coll Comp Sci Dept Comp Sci Abha Saudi Arabia Gandhi Inst Technol Adv GITA Dept Comp Sci & Engn Bhubaneswar Odisha India Dr MGR Educ & Res Inst Dept Comp Sci & Engn Chennai Tamil Nadu India

Hearing aid is an acoustic device which is worn by hearing loss people. To compensate the different types of hearing loss, it is necessary to selectively amplify sounds at required frequencies. The main aim of the hearing aid is to selectively remove the noise signal such that the processed sound matches ones audiogram. To achieve this, the decimation filter in hearing aids can be design using multiplier less architecture which should be able to adjust sound levels at arbitrary frequencies within a given spectrum. In hearing aids, decimation filter plays a key role. This paper presents a low complexity design of a digital finite impulse response (FIR) filter for digital hearing aid application. This paper proposed approximate 4:2 compressor adders in memory less DA based FIR filter architecture. In DA architecture the area of the ROM increases gradually when filter order is increased. Memory less DA is designed using compressor adders is a solution to decrease the power consumption and area of the FIR filters and makes the area and power reduction for hearing aid application. The proposed DA based FIR filter architecture is synthesized on 90 nm technology using Synapsis Application Specific Integrated circuit design compiler. The proposed architecture has 45% reduction in area delay product when distinguish with systolic architecture and 10% less ADP when compare with OBC DA architecture. The proposed design is also implemented Field Programmable Gate Array and the results shows that the proposed architecture has less slices than best existing designs. The proposed architecture is used in decimation filter of hearing aids applications using matlab simulink, which removes the unwanted signal.

关键词： Speech signal Decimation filter distributed arithmetic Hearing aid FIR filter Half band filter

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A parallel arithmetic for hardware realization of digital filters

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MICROELECTRONICS JOURNAL 2019年 83卷 131-136页

作者： Fan, Chunxiao Li, Fu Cao, Xin Qian, Biao Song, Peipei Hefei Univ Technol Sch Comp Sci & Informat Engn Hefei 230601 Anhui Peoples R China Xidian Univ Sch Artificial Intelligence Xian 710071 Shaanxi Peoples R China Northwest Univ Sch Informat Sci & Technol Xian 710069 Shaanxi Peoples R China

distributed arithmetic (DA) is a classic technique for the hardware realization of digital filters. We present a novel parallel arithmetic operation to overcome two drawbacks in existing DA and DA-based methods: 1) the throughput is difficult to improve and 2) hardware resource consumption increases exponentially with the length of filter order. The fundamental difference between the proposed and existing methods is that the proposed method factors the filter coefficients to find several simple basic operations, which can circumvent the inherent bit-serial nature of DA methods and achieve the whole operation in one clock cycle. Additionally, the number of possible basic operations increases linearly with the length of filter order, which means we can relieve the exponentially increasing hardware resource consumption. The proposed method is evaluated through two experiments, and the results demonstrate that the proposed technique outperforms existing DA and DA-based methods in terms of throughput and resource consumption.

关键词： distributed arithmetic Digital filter Convolution Hardware realization VLSI

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An on-sensor bit-serial column-parallel processing architecture for high-speed discrete Fourier transform

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2006年第8期53卷 642-646页

作者： Eki, Tatsuya Kawahito, Shoji Tadokoro, Yoshiaki Yamatake Corp Adv Automat Co Fujisawa 2518522 Japan Shizuoka Univ Elect Res Inst Hamamatsu Shizuoka 4328011 Japan Toyohashi Univ Technol Dept Informat & Comp Sci Toyohashi Aichi 4418580 Japan

This brief presents a discrete Fourier transform (DFT) processor based on a bit-serial column-parallel processing architecture suitable for integrating it on CMOS image sensors. Using a column-parallel A/D converter (ADC) array, column-line sensor outputs of the two-dimensional image array are digitized. The ADC outputs are sliced to one bit and are given to the bit-serial column-parallel DFT processor from the MSB to the LSB. A high-speed and cost-effective implementation can be expected. In the case of 256 x 256-point DFT for 8-b image data, the processing time is estimated to be 2 ins at a clock frequency of 100 MHz, which corresponds to the 500-frames/s real-time processing.

关键词： CMOS image sensor discrete Fourier transform (DFT) distributed arithmetic functional image sensor

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FACCU: Enable Fast Accumulation for High-Speed DSP Systems

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2022年第12期69卷 4634-4638页

作者： Wang, Meiqi Cheng, Xin Zou, Dingyang Wang, Zhongfeng Nanjing Univ Sch Elect Sci & Engn Nanjing 210023 Peoples R China

A number of fast accumulation (FACCU) designs are proposed for one of the essential components in DSP systems, the accumulator, to largely boost the DSP's maximum attainable processing speed. By leveraging the unique features of the accumulator, the loop-incorporated critical path is reduced to as short as one or two full adders without degrading the sampling rate, thus efficiently addressing the system bottleneck caused by the recursive loop in accumulation. Based on this innovation, several highly scalable FACCU architectures are developed to meet various high-speed requirements with minimal overhead. Moreover, novel system-level co-optimization skills are developed in FACCU variants for two commonly used subsystems involving accumulators (the AdderTree-SA and the distributed arithmetic architecture) to achieve the best trade-off between area and speed, which have not been well investigated in previous works. Implementation results under the SMIC 55nm technology demonstrate that the proposed FACCU designs have great superiority in critical path delay, area, and latency compared with both prior art and the accumulators deeply optimized with the EDA tool. The application-level evaluations are also conducted for an FACCU-incorporated hardware accelerator of image processing network, demonstrating that the developed FACCU can efficiently improve the throughput in a real system.

关键词： High-speed DSP accumulator hardware accelerator multiply-accumulate (MAC) distributed arithmetic

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High performance area efficient DA based FIR filter for concurrent decision feedback equalizer

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INTERNATIONAL JOURNAL OF SPEECH TECHNOLOGY 2020年第2期23卷 297-303页

作者： Vijetha, K. Naik, B. Rajendra Osmania Univ Dept Elect Engn Hyderabad Telangana India

In this paper we proposed a novel distributed arithmetic (DA) based block FIR filters for design of decision feed back equalizers. Here a block FIR filter is designed using DA architecture and is implement for DFE architecture. By introducing block FIR filter architecture the throughput rate for the design is increased. The proposed distributed arithmetic architecture is implemented in application specific integrated circuit (ASIC) Synopsis design compiler tool using SAED 90 nm technology. The application of decision feed back equalizer is implemented in Matlab Simulink and Xilinx system generator tool. The obtained results shows 71% less area delay product (ADP) and 65% less energy delay product (EDP) when compared with the existing architecture and the performance of the design is very high. By using proposed DA based DFE architecture the ISI noises can be removed and is well suited for digital communication systems.

关键词： FIR filter distributed arithmetic Feed-back filter Feed-forward filter equalizer Signal transmission

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