检索结果-内蒙古大学图书馆

Embedded distributed arithmetic based quaternions multiplier of paraunitary filter bank for lossless-to-lossy image coding

引用

MICROPROCESSORS AND MICROSYSTEMS 2017年第Jul.期52卷 510-522页

作者： Petrovsky, N. A. Rybenkov, E. V. Petrovsky, A. A. Belarusian State Univ Informat & Radioelect P Browki Str 6 Minsk 220013 BELARUS

This paper presents a systematic design of the integer-to-integer invertible quaternionic multiplier based on the block-lifting structure and pipelined embedded processor of the given multiplier using distributed arithmetic (DA) as a block of M-band linear phase paraunitary filter banks (LP PUFB) based on the quaternionic algebra (Q-PUFB) for the lossy-to-lossless image coding. A bank Q-PUFB based on the DA block lifting structure reduces the number of rounding operations and has a regular layout. Since the block lifting structures with rounding operations can implement the integer-to-integer transform (Int-Q-PUFB). (C) 2017 Elsevier B.V. All rights reserved.

关键词： Quatemion Filter bank distributed arithmetic FPGA Embedded processor

来源：评论

学校读者我要写书评

暂无评论

Improved convergent distributed arithmetic based low complexity pipelined least-mean-square filter

引用

IET CIRCUITS DEVICES & SYSTEMS 2018年第6期12卷 792-801页

作者： Khan, Mohd Tasleem Shaik, Rafi Ahamed Matcha, Surya Prakash Indian Inst Technol Guwahati Dept Elect & Elect Engn Gauhati India

This study presents an improved convergent distributed arithmetic (DA)-based low complexity pipelined least-mean-square filter. The concept is based on a convex combination of two adaptive filters (ADFs) where the convergence performance of the combined filter is adjusted by the step-sizes of ADFs. The proposed technique replaced two ADF units by a single unit of the DA-based ADF. Further reduction in hardware complexity is achieved by sharing the filter partial products. Moreover, a bit-level coefficient update unit is employed to minimise its hardware complexity. In addition, a novel low-cost strategy is presented to improve the convergence performance of the proposed filter by comparing the time-window corresponding to the maximum correlation of delayed error signals Compared with the best existing scheme, the proposed design offers 46.42% fewer adders, 36.69% fewer registers and 18.75% fewer multiplexers for a 64th-order filter. Application specific integrated circuit synthesis results show that the proposed design occupies 37.10% less chip-area and consumes 24.79% less power. In addition, the proposed design provides 20.35% less area-delay-product and 4.76% less energy-per-sample for 64th order with the fourth-order base unit over the best existing scheme.

关键词： application specific integrated circuits low-power electronics adaptive filters integrated circuit design distributed arithmetic least mean squares methods convergent distributed arithmetic least-mean-square filter convex combination adaptive filters combined filter ADF units hardware complexity filter partial products 64th-order filter fourth-order base unit application specific integrated circuit synthesis

来源：评论

学校读者我要写书评

暂无评论

New distributed arithmetic algorithm and its application to IDCT

引用

IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS 1999年第4期146卷 159-163页

作者： Chang, TS Chen, C Jen, CW Natl Chiao Tung Univ Dept Elect Engn Hsinchu 300 Taiwan

distributed arithmetic (DA) has been widely used to implement inner product computations with a fixed input. Conventional ROM-based DA suffers from large ROM requirements. A new DA algorithm is proposed that expands the fixed input instead of the variable input into bit level as in ROM-based DA. Thus the new DA algorithm can take advantage of shared partial sum-of-products and sparse nonzero bits in the fixed input to reduce the number of computations. Unlike ROM-based DA that stores the precomputed results the new DA algorithm uses a predefined structure to compute results. When applied to a 1-D eight-point DCT system the new DA algorithm only needs 30% of hardware area and has faster speed as compared with ROM-based DA. To illustrate the efficiency of the proposed algorithm a 2-D IDCT chip was implemented using 0.8 mu m SPDM CMOS technology. The chip with size 4575 x 5525 mu m can deliver a processing rate of 50 Mpixels per second.

关键词： CMOS digital integrated circuits IDCT shared partial sum-of-products ROM-based DA SPDM CMOS technology 0.8 micron discrete cosine transforms processing rate 1D eight-point DCT system bit level hardware area distributed arithmetic inverse DCT variable input VLSI digital signal processing chips sparse nonzero bits inner product computations distributed arithmetic algorithm

来源：评论

学校读者我要写书评

暂无评论

A modular approach to the computation of convolution sum using distributed arithmetic principles

引用

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING 1999年第1期46卷 92-96页

作者： Lim, KP Premkumar, AB Nanyang Technol Univ Sch Appl Sci Singapore 2263 Singapore

Inner product evaluation can be considered to be basic to all digital signal processing algorithms. distributed arithmetic (DA) is a bit serial memory-oriented method that implements inner products. In DA, memory increases exponentially as the number of coefficients increases, This deters the use of DA in the implementation of DSP algorithms. This paper explores the possibility of combining DA principles with the residue number system (RNS) to exploit the advantages of both. ii new technique for the computation of the inner product in the RNS domain using modular multipliers and DA principles is proposed, The resulting architecture is elegant, uses minimum memory and adders, and hence is VLSI efficient, The proposed architecture is extremely efficient in terms of speed and does not involve conversion of data into residues although computation is performed in residue domain.

关键词： distributed arithmetic modular multiplier residue number system

来源：评论

学校读者我要写书评

暂无评论

Fast implementation of forward robot kinematics of position with distributed arithmetic architecture

引用

IEEE TRANSACTIONS ON SYSTEMS MAN AND CYBERNETICS PART A-SYSTEMS AND HUMANS 1999年第3期29卷 325-332页

作者： Mertzios, BG Grigoriadis, GK Democritus Univ Thrace Dept Elect & Comp Engn Automat Control Syst Lab GR-67100 Xanthi Greece

This paper refers to the fast implementation of the forward kinematic equations of position of robotics manipulators, using a distributed arithmetic-based pipeline architecture. The building blocks of this pipeline architecture are the distributed arithmetic-based circuits that implement the matrix-vector multiplications involved in the calculation of the forward kinematics of position. The matrix-vector multiplications are implemented in the distributed arithmetic technique by using auxiliary binary functions, which are stored in look-up tables. The digit-serial configuration of the proposed implementation is described. The serial and the parallel configurations may result as special extreme cases of the digit-serial configuration.

关键词： digit-serial configuration distributed arithmetic forward kinematics of position matrix-matrix-multiplication (MMM) matrix-vector-multiplication (MVM) pipelining

来源：评论

学校读者我要写书评

暂无评论

High-Throughput, Area-Efficient Architecture of 2-D Block FIR Filter Using distributed arithmetic Algorithm

引用

CIRCUITS SYSTEMS AND SIGNAL PROCESSING 2019年第3期38卷 1099-1113页

作者： Kumar, Prashant Shrivastava, Prabhat Chandra Tiwari, Manish Mishra, Ganga Ram MNNIT Dept Elect & Commun Engn Allahabad 211004 Uttar Pradesh India Amity Univ Lucknow Campus Lucknow Uttar Pradesh India

This paper proposes a new architecture of 2-D block FIR filter using distributed arithmetic (DA) algorithm, which is known for the efficient design of multiply and accumulate block. Hardware-based architecture is proposed for DA lookup table (DA-LUT) that makes the architecture of 2-D FIR filter reconfigurable. Further, due to block processing, sharing takes place among DA-LUTs at various stages. Thus, a common DA-LUT may be designed for block inputs which reduce the hardware complexity for DA-LUT. Furthermore, memory overlapping is used to reduce the systolic architectures in proposed design over existing designs. For higher-order 2-D FIR filter, the complexity of DA-LUT is reduced by dividing the internal block into parallel and small blocks. With the help of ASIC synthesis results, a comparative analysis of proposed design with the earlier reported designs is presented, and it is shown that the proposed design leads to significant improvements in various performance parameters.

关键词： 2-D block FIR filtering distributed arithmetic Multiplier-less filter VLSI design

来源：评论

学校读者我要写书评

暂无评论

DCT implementation with distributed arithmetic

引用

IEEE TRANSACTIONS ON COMPUTERS 2001年第9期50卷 985-991页

作者： Yu, S Swartzlander, EE Intel Corp Austin TX 78746 USA Univ Texas Dept Elect & Comp Engn Austin TX 78712 USA

This paper presents an efficient method for implementing the Discrete Cosine Transform (DCT) with distributed arithmetic. While conventional approaches use the original DCT algorithm or the even-odd frequency decomposition of the DCT algorithm, the proposed architecture uses the recursive DCT algorithm and requires less area than the conventional approaches, regardless of the memory reduction techniques employed in the ROM Accumulators (RACs). An efficient architecture for implementing the scaled DCT with distributed arithmetic is also proposed. The new architecture requires even less area while keeping the same structural regularity for an easy VLSI implementation. A comparison of synthesized DCT processors shows that the proposed method reduces the hardware area of regular and scaled DCT processors by 17 percent and 23 percent, respectively, relative to a conventional design, With the row-column decomposition method, the proposed architectures can be easily extended to compute the two-dimensional DCT required in many image compression applications such as HDTV.

关键词： Discrete Cosine Transform distributed arithmetic recursive DCT algorithm

来源：评论

学校读者我要写书评

暂无评论

A memory and area-efficient distributed arithmetic based modular VLSI architecture of 1D/2D reconfigurable 9/7 and 5/3 DWT filters for real-time image decomposition

引用

JOURNAL OF REAL-TIME IMAGE PROCESSING 2020年第5期17卷 1421-1446页

作者： Chakraborty, Anirban Banerjee, Ayan Indian Inst Engn Sci & Technol Elect & Telecommun Engn Dept Sibpur Howrah India

In this article, we have proposed the internal architecture of a dedicated hardware for 1D/2D convolution-based 9/7 and 5/3 DWT filters, exploiting bit-parallel 'distributed arithmetic' (DA) to reduce the computation time of our proposed DWT design while retaining the area at a comparable level to other recent existing designs. Despite using memory extensive bit-parallel DA, we have successfully achieved 90% reduction in the memory size than that of the other notable architectures. Through our proposed architecture, both the 9/7 and 5/3 DWT filters can be realized with a selection input, mode. With the introduction of DA, we have incorporated pipelining and parallelism into our proposed convolution-based 1D/2D DWT architectures. We have reduced the area by 38.3% and memory requirement by 90% than that of the latest remarkable designs. The critical-path delay of our design is almost 50% than that of the other latest designs. We have successfully applied our prototype 2D design for real-time image decomposition. The quality of the architecture in case of real-time image decomposition is measured by 'peak signal-to-noise ratio' and 'computation time', where our proposed design outperforms other similar kind of software- and hardware-based implementations.

关键词： DWT distributed arithmetic Memory efficient Digital VLSI design Parallelism Image decomposition PSNR

来源：评论

学校读者我要写书评

暂无评论

Modified Sliding-Block distributed arithmetic with Offset Binary Coding for Adaptive Filters

引用

JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2011年第1期63卷 153-163页

作者： Huang, Walter Anderson, David V. Georgia Inst Technol Sch Elect & Comp Engn Atlanta GA 30332 USA

An efficient way for computing the response of an adaptive digital filter is to use sliding-block distributed arithmetic (SBDA). However, a disadvantage of distributed arithmetic is the amount of memory utilized. By encoding the memory tables in offset binary code (OBC), the size of the memory tables is reduced by half, while the computational workload remains unchanged. By modifying the computational flow, the computational workload can be reduced by almost by half at the expense of slightly more memory. This modified SBDA structure is called SBDA-OBC. It has memory requirements 25-50% lower than SBDA depending on the size of the sub-filter. In terms of the computational workload, SBDA-OBC is most advantageous for large sub-filters and when the filter is split into few sub-filters. In this case, the computational workload is reduced almost in half.

关键词： Adaptive filtering distributed arithmetic

来源：评论

学校读者我要写书评

暂无评论

NEW REALIZATION TECHNIQUE OF HIGH-SPEED DISCRETE FOURIER-TRANSFORM DESCRIBED BY distributed arithmetic

引用

IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES 1983年第6期130卷 177-182页

作者： SIU, WC CHEN, CF Department of Electronics Chinese University of Hong Kong London UK Department of Electrical Engineering Imperial College of Science and Technology London UK

This paper presents the results of a study using distributed arithmetic on a microprocessor to implement a prime-number-based discrete Fourier transform (DFT). The matrix equation of the DFT can be reordered in a convolution form suitable for distributed arithmetic. Further simplification of the equation can be achieved by noting some simple properties of number theory and the DFT. It was found that the total computation time for a 61-point DFT, using a 2 MHz clock 6800 microprocessor, was only 3.6 ms, and the computation time increases directly in proportion to the number of points in the DFT. This fast realisation technique should be suitable both for microprocessor-based systems and for the direct hardware implementation.

关键词： direct hardware implementation distributed arithmetic high-speed discrete Fourier transform Digital arithmetic methods matrix equation digital arithmetic Fourier transforms number theory 6800 microprocessor

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：