Improved convergent distributed arithmetic based low complexity pipelined least-mean-square filter

作     者：Khan, Mohd Tasleem Shaik, Rafi Ahamed Matcha, Surya Prakash 

作者机构：Indian Inst Technol Guwahati Dept Elect & Elect Engn Gauhati India 

出 版 物：《IET CIRCUITS DEVICES & SYSTEMS》 (IET Circuits Devices Syst.)

年 卷 期：2018年第12卷第6期

页      面：792-801页

核心收录：

学科分类：0808[工学-电气工程] 08[工学] 

基　　金：Special Manpower Development Programme for Chip to System Design (SMDP-C2SD) - the Ministry of Electronics & Information Technology (MeitY)  Government of India 

主　　题：application specific integrated circuits low-power electronics adaptive filters integrated circuit design distributed arithmetic least mean squares methods convergent distributed arithmetic least-mean-square filter convex combination adaptive filters combined filter ADF units hardware complexity filter partial products 64th-order filter fourth-order base unit application specific integrated circuit synthesis 

摘      要：This study presents an improved convergent distributed arithmetic (DA)-based low complexity pipelined least-mean-square filter. The concept is based on a convex combination of two adaptive filters (ADFs) where the convergence performance of the combined filter is adjusted by the step-sizes of ADFs. The proposed technique replaced two ADF units by a single unit of the DA-based ADF. Further reduction in hardware complexity is achieved by sharing the filter partial products. Moreover, a bit-level coefficient update unit is employed to minimise its hardware complexity. In addition, a novel low-cost strategy is presented to improve the convergence performance of the proposed filter by comparing the time-window corresponding to the maximum correlation of delayed error signals Compared with the best existing scheme, the proposed design offers 46.42% fewer adders, 36.69% fewer registers and 18.75% fewer multiplexers for a 64th-order filter. Application specific integrated circuit synthesis results show that the proposed design occupies 37.10% less chip-area and consumes 24.79% less power. In addition, the proposed design provides 20.35% less area-delay-product and 4.76% less energy-per-sample for 64th order with the fourth-order base unit over the best existing scheme.