In this paper, a low-complexity pipelined adaptive FIR filter is designed using distributed arithmetic (DA) architecture for signal processing applications. Generally adaptive filters will occupy more area and power c...
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In this paper, a low-complexity pipelined adaptive FIR filter is designed using distributed arithmetic (DA) architecture for signal processing applications. Generally adaptive filters will occupy more area and power consumption because of using memories in the filters for partial product (PP) generation. To get rid of this, We use the pipeline concept to reduce the registers in the filters and also to reduce the area further compressor adders are used in the adaptive filter architectures instead of using normal adders. With these two concepts the area and power consumption of the adaptive filters will be reduced. The proposed design is coded in Verilog HDL language and synthesized in Synapsis design compiler tool with SAED 90 nm technology for finding the area, power, minimum sampling period, maximum sampling frequency, area delay product (ADP), power delay product (PDP). By using proposed adaptive filter we can design and implement higher order filters more easily and also the complexity of the proposed design is very less when compared with the existing designs. When we observe the synthesis results the proposed design will occupy 30% less area when compared with the two memories based existing architecture. Also the power consumption is 25% less when compared with the block based adaptive fillers. The ADP and PDP of the proposed design is very less when compared with existing architectures. The proposed design is well suited for signal processing application designs such as adaptive decision feed back equalizers for removing the signal noises and inter symbol interference, hearing aids, ECG signal analysis and software defined radio.
distributed arithmetic is a popular method for implementing digital FIR filters on FPGAs. One essential optimization method is the division of large look-up tables (LUTs) into smaller partial LUTs by using additional ...
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ISBN:
(纸本)9781467357623;9781467357609
distributed arithmetic is a popular method for implementing digital FIR filters on FPGAs. One essential optimization method is the division of large look-up tables (LUTs) into smaller partial LUTs by using additional adders. Previous work indicates, that the size of these partial LUTs should be chosen to the LUT input size of the FPGA which was 4 for a long time. Nowadays, modern FPGAs offer 6-input LUTs which can be configured to two 5-input LUTs with shared inputs. This paper investigates the optimal input size of partial LUTs on FPGAs with 4-input and 5/6-input LUTs. On FPGAs with 4-input LUTs, it turnes out that only in 62% of the cases (out of 220), a LUT input size of 4 leads to the best implementation. However, the slice overhead is 6.3% on average for the other cases. On FPGAs with 5/6-input LUTs, the least slice overhead (10% on average) is paid when the LUT input size is chosen to 6. However, it was shown that a resource reduction of up to 32% can be achieved when all input sizes in the range 4...7 are evaluated. Using the best partial LUT size, slice reductions of over 50% on average compared to Xilinx Coregen could be achieved for Virtex 6 FPGAs.
The DCT transform has been extensively used in various digital image coding schemes and image compression standards. In this pap er, VHDL implementation of Odd Discrete Cosine Transform (ODCT-II) coefficient computati...
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ISBN:
(纸本)9781479916054
The DCT transform has been extensively used in various digital image coding schemes and image compression standards. In this pap er, VHDL implementation of Odd Discrete Cosine Transform (ODCT-II) coefficient computation using independent update algorithm is discussed. By independent, we mean ODCT coefficient computation of shifted data sequence doesn't require ODST coefficients of previous data. The running input data sequence is sampled using a rectangular window. The independent update algorithm is used to compute the transform coefficients of the shifted sequence using distributed arithmetic (DA) approach. The design is synthesized using ISE 10.1 and implemented on Vertex 4. Implementation shows that DA based approach is more efficient in terms of device utilization
An architecture for a dynamically run-time reconfigurable finite impulse response (FIR) filter is presented in this work. It is based on distributed arithmetic (DA) combined with a look- up table (LUT) reduction techn...
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ISBN:
(纸本)9781467357623;9781467357609
An architecture for a dynamically run-time reconfigurable finite impulse response (FIR) filter is presented in this work. It is based on distributed arithmetic (DA) combined with a look- up table (LUT) reduction technique which allows the direct mapping to reconfigurable LUTs (CFGLUT) of the latest Xilinx FPGAs. The resulting FIR filter can be reconfigured with arbitrary coefficients which are only limited by their length and word size. The number of filter instances for reconfiguration is only limited by the block memory of the FPGA which typically allows hundreds of different configurations. The proposed reconfigurable architecture consumes 16% less slices on average than a fixed coefficient DA filter generated by Xilinx Coregen. As the direct mapping to CFGLUTs leads to invalid filter output during reconfiguration, an alternative architecture is proposed which avoids this limitation at the cost of 19% more slice resources on average. Using a parallel reconfiguration scheme, reconfiguration times of about 100 ns could be achieved.
Hearing aid is an acoustic device which is worn by hearing loss people. To compensate the different types of hearing loss, it is necessary to selectively amplify sounds at required frequencies. The main aim of the hea...
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Hearing aid is an acoustic device which is worn by hearing loss people. To compensate the different types of hearing loss, it is necessary to selectively amplify sounds at required frequencies. The main aim of the hearing aid is to selectively remove the noise signal such that the processed sound matches ones audiogram. To achieve this, the decimation filter in hearing aids can be design using multiplier less architecture which should be able to adjust sound levels at arbitrary frequencies within a given spectrum. In hearing aids, decimation filter plays a key role. This paper presents a low complexity design of a digital finite impulse response (FIR) filter for digital hearing aid application. This paper proposed approximate 4:2 compressor adders in memory less DA based FIR filter architecture. In DA architecture the area of the ROM increases gradually when filter order is increased. Memory less DA is designed using compressor adders is a solution to decrease the power consumption and area of the FIR filters and makes the area and power reduction for hearing aid application. The proposed DA based FIR filter architecture is synthesized on 90 nm technology using Synapsis Application Specific Integrated circuit design compiler. The proposed architecture has 45% reduction in area delay product when distinguish with systolic architecture and 10% less ADP when compare with OBC DA architecture. The proposed design is also implemented Field Programmable Gate Array and the results shows that the proposed architecture has less slices than best existing designs. The proposed architecture is used in decimation filter of hearing aids applications using matlab simulink, which removes the unwanted signal.
In this paper we proposed a novel distributed arithmetic (DA) based block FIR filters for design of decision feed back equalizers. Here a block FIR filter is designed using DA architecture and is implement for DFE arc...
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In this paper we proposed a novel distributed arithmetic (DA) based block FIR filters for design of decision feed back equalizers. Here a block FIR filter is designed using DA architecture and is implement for DFE architecture. By introducing block FIR filter architecture the throughput rate for the design is increased. The proposed distributed arithmetic architecture is implemented in application specific integrated circuit (ASIC) Synopsis design compiler tool using SAED 90 nm technology. The application of decision feed back equalizer is implemented in Matlab Simulink and Xilinx system generator tool. The obtained results shows 71% less area delay product (ADP) and 65% less energy delay product (EDP) when compared with the existing architecture and the performance of the design is very high. By using proposed DA based DFE architecture the ISI noises can be removed and is well suited for digital communication systems.
This brief presents a decimation filter for hearing aid application using distributed arithmetic (DA) approach. In this paper, we propose a reconfigurable offset-binary code (OBC) DA based finite impulse response (FIR...
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This brief presents a decimation filter for hearing aid application using distributed arithmetic (DA) approach. In this paper, we propose a reconfigurable offset-binary code (OBC) DA based finite impulse response (FIR) filter with a shared look-up table (LUT) updating scheme. The size of the LUTs in DA increases exponentially with the order of filters. Shared LUT based DA structure is a solution to reduce this large memory requirement for higher order filters. The proposed shared LUT updating scheme uses LUT partitioning in which coefficients are spilt into small length vectors and it ensures a drastic reduction in the size of LUTs. The proposed DA filter is synthesized on CMOS 90 nm technology using Synapsis ASIC Design Compiler. The proposed design achieves high speed at a reduced area-delay product (ADP) when compared with recent designs. The proposed architecture is implemented and tested on Virtex 5vsx95-1ff1136 FPGA and the results show that the proposed design involves less number of slices and offers high speed than existing designs. A three-stage decimation filter of hearing aids is designed with the proposed FIR filter and is implemented on the target device by Matlab simulink and Xilinx system generator.
This paper deals with less delay efficient multiplier and accumulator unit for inner product, filtering [3] applications, convolution, image and video processing applications etc., Multiply and Accumulate unit plays a...
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ISBN:
(纸本)9781728172231
This paper deals with less delay efficient multiplier and accumulator unit for inner product, filtering [3] applications, convolution, image and video processing applications etc., Multiply and Accumulate unit plays and important role in Digital signal processor. On designing this consumes large area because it contains partial products so distributed arithmetic is considered to improve the speed but for each added input size of the ROM increases exponentially so offset binary coding preferred. By using floating point Offset binary coding complete speed of the processor will be increased. These designs are simulated and synthesized with Xilinx 14.7 ISE software. It achieves best area and less delay result when compared with other designs.
distributed arithmetic (DA) is a classic technique for the hardware realization of digital filters. We present a novel parallel arithmetic operation to overcome two drawbacks in existing DA and DA-based methods: 1) th...
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distributed arithmetic (DA) is a classic technique for the hardware realization of digital filters. We present a novel parallel arithmetic operation to overcome two drawbacks in existing DA and DA-based methods: 1) the throughput is difficult to improve and 2) hardware resource consumption increases exponentially with the length of filter order. The fundamental difference between the proposed and existing methods is that the proposed method factors the filter coefficients to find several simple basic operations, which can circumvent the inherent bit-serial nature of DA methods and achieve the whole operation in one clock cycle. Additionally, the number of possible basic operations increases linearly with the length of filter order, which means we can relieve the exponentially increasing hardware resource consumption. The proposed method is evaluated through two experiments, and the results demonstrate that the proposed technique outperforms existing DA and DA-based methods in terms of throughput and resource consumption.
We present novel architectures for the modified K-best algorithm and its very-large-scale integration implementation for spatially multiplexed wireless multiple-input multiple-output systems. The objective was to prop...
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We present novel architectures for the modified K-best algorithm and its very-large-scale integration implementation for spatially multiplexed wireless multiple-input multiple-output systems. The objective was to propose a simplified architecture based on the algorithm and to significantly improve the suitability for hardware implementation. Two different architecture designs were proposed: a distributed arithmetic-based tree-search detector and a breadth-first search sphere detector. The implementations were performed to obtain a configurable architectural solution for different antenna configurations and constellations. The synthesis analysis shows that the proposed architectures achieve a throughput of > 500 Mbps with reduced hardware complexity compared to previously reported architectures. (C) 2020 Elsevier B.V. All rights reserved.
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