Multithreshold decoder (MTD) is the simplest type of majority decoder that decodes self-orthogonal codes. Low computational complexity and simple decoding hardware implementation of multithreshold decoders allow using...
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ISBN:
(纸本)9781509009732
Multithreshold decoder (MTD) is the simplest type of majority decoder that decodes self-orthogonal codes. Low computational complexity and simple decoding hardware implementation of multithreshold decoders allow using them in high speed communication systems and data storage systems that require decoding information at speeds above 1 Gbit/s. A high-speed software binary multithreshold decoder using a modern computing power of the graphics processing unit (GPU) is considered. Such software implementation of MTD helps to decode several hundred blocks received from the channel completely parallel and independent from each other. It is shown that the speed of software MTD based on GPU GTX 970 can reach 350 Mbit/s.
Multithreshold decoders (MTD) of self-orthogonal codes (SOC) for erasure channels implementing errorcorrection methods based on searching global extremum of functions in discrete spaces are considered. To increase th...
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ISBN:
(纸本)9781728117393
Multithreshold decoders (MTD) of self-orthogonal codes (SOC) for erasure channels implementing errorcorrection methods based on searching global extremum of functions in discrete spaces are considered. To increase the efficiency of erasure recoveries the concatenated codes comprising inner SOC and outer codes being simple for decoding such as parity-check codes, Hamming codes or BCH codes are offered. The usage of the codes offered provides efficient erasure recovery when operating near channel capacity with linear decoder complexity. The questions of high-throughput software MTD implementation recovering erasures using GPU are considered. The MTD versions developed are shown to be able to perform data flow decoding with the rate of several hundred MB/s using GPU.
The present paper has considered multithreshold decoders for self-orthogonal codes providing a near-optimal efficiency of the errorcorrection under linear computational complexity. New divergence principle used withi...
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ISBN:
(纸本)9781538605851
The present paper has considered multithreshold decoders for self-orthogonal codes providing a near-optimal efficiency of the errorcorrection under linear computational complexity. New divergence principle used within construction and decoding convolutional codes has been discussed. The paper has shown that usage of such principle allows significantly approximating an area of the decoder effective operation to the channel capacity. Application of obtained self-orthogonal codes within construction of concatenated convolutional codes where parity-check codes are used as the outer codes has been indicated, as well as simulation results for the obtained concatenated construction have been represented.
This paper provides a soft Bose-Chaudhuri-Hochquenghem (BCH) decoder chip with soft information from the LDPC decoder for the DVB-S2 system. In contrast with the hard BCH decoder, the proposed soft BCH decoder that de...
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This paper provides a soft Bose-Chaudhuri-Hochquenghem (BCH) decoder chip with soft information from the LDPC decoder for the DVB-S2 system. In contrast with the hard BCH decoder, the proposed soft BCH decoder that deals with least reliable bits can provide much lower complexity with similar error-correcting performance. Moreover, the error locator evaluator is proposed to evaluate error locations without the Chien search for higher throughput, and the Bjorck-Pereyra error magnitude solver (BP-EMS) is presented to improve decoding efficiency and hardware complexity. The chip measurement results reveal that our proposed soft (32400, 32208) BCH decoder for DVB-S2 system can achieve 314.5 Mb/s with a gate-count of 26.9 K in standard 90 nm 1P9M CMOS technology. Extended for fully supporting 21 modes in the DVB-S2 system, our approach can achieve 300 MHz operation frequency with a gate-count of 32.4 K.
Reed-Solomon (RS) codes are commonly utilized in magnetic recording systems to correct error bursts. Soft-output Viterbi algorithm (SOYA) is a commonly used detector to provide soft information to error-correcting dec...
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ISBN:
(纸本)9781479923588
Reed-Solomon (RS) codes are commonly utilized in magnetic recording systems to correct error bursts. Soft-output Viterbi algorithm (SOYA) is a commonly used detector to provide soft information to error-correcting decoders. We propose a novel architecture of multilevel interleaved RS coding scheme that not only provides better performance but also has less complexity than an equivalent RS code. This architecture implements an error event detector using the soft information generated by the SOYA detector.
In Multi-Level Cell (MLC) memories, multiple bits of information are packed within the cell to enable higher capacity and lower cost of manufacturing compared to those of the single-level cell flash. However, because ...
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In Multi-Level Cell (MLC) memories, multiple bits of information are packed within the cell to enable higher capacity and lower cost of manufacturing compared to those of the single-level cell flash. However, because of heavy information packing, MLC memories suffer from several error sources including inter-cell interference, retention error, and random telegraph noise which make their lifetime shorter. Having so many error sources that are statistically hard to characterize makes it challenging to properly derive the underlying probability distribution of the sensed threshold voltage, which is vital for finding optimal decision rules to secure better detection performance and hence better lifetime. Although several recent works have already considered this problem, they mostly recourse to few loose assumptions that are far from being realistic. In this study, a more comprehensive/general analysis is conducted to derive the probability density function of the final sensed voltage, and through realistic simplifications, closed form expressions are presented. Extensive computer simulations corroborate the accuracy of the derived analytical expressions, and we think they shall be essential for accurately estimating the reliability and the overall lifetime of modern MLC memories. (C) 2019 Elsevier B.V. All rights reserved.
The applications of non-square binary matrices span many domains including mathematics, error-correction coding, machine learning, data storage, navigation signals, and cryptography. In particular, they are employed i...
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The applications of non-square binary matrices span many domains including mathematics, error-correction coding, machine learning, data storage, navigation signals, and cryptography. In particular, they are employed in the McEliece and Niederreiter public-key cryptosystems. For the parity check matrix of these cryptosystems, a systematic non-square binary matrix H with dimensions m x n, n > m, m = n - k, there exist 2m((n -m) )distinct inverse matrices. This article presents an algorithm to generate these matrices as well as a method to construct a random inverse matrix. Then it is extended to non-square matrices in arbitrary fields. This overcomes the limitations of the Moore-Penrose and Gauss-Jordan methods. The application to public-key cryptography is also discussed.
Serial Concatenation of Interleaved Codes (SCICs) is emerging as a promising technology to improve the physical layer (PHY) performance of modern wireless communication systems in terms of bit-error rate (BER), mainly...
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ISBN:
(纸本)9781467311496
Serial Concatenation of Interleaved Codes (SCICs) is emerging as a promising technology to improve the physical layer (PHY) performance of modern wireless communication systems in terms of bit-error rate (BER), mainly due to their outstanding coding gains and feasible decoding complexities. For their channel coding performance, an interleaver is a critical component since the Minimum Hamming Distance (MHD) between legitimated permutations of the encoded bit sequence is directly influenced by the interleaver design. In this treatise, the construction of permutation mapping for SCICs is considered based on quadratic congruence, and the results are compared with the system using matrix-based block interleavers where the randomization is performed by storing and looking up elements in a matrix configuration. The performance evaluations are carried out in terms of BER for Single-Input Single-Output (SISO) and Multiple Input Single-Output (MISO) wireless communication systems in a femtocell propagation environment. The results reveal that employing quadratic interleavers yield lower BERs at both waterfall and error-floor regions, compared with the block interleavers.
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