检索结果-内蒙古大学图书馆

fault coverage AND TEST LENGTH ESTIMATION FOR RANDOM PATTERN TESTING

IEEE TRANSACTIONS ON COMPUTERS 1995年第2期44卷 234-247页

作者： MAJUMDAR, A VRUDHULA, SBK UNIV ARIZONA DEPT ELECT & COMP ENGNTUCSONAZ 85721

fault coverage and test length estimation in circuits under random test is the subject of this paper. Testing by a sequence of random input patterns is viewed as sequential sampling of faults from a given fault universe. Based on this model, the probability mass function (pmf) of fault coverage and expressions for all its moments are derived. This provides a means for computing estimates of fault coverage as well as determining the accuracy of the estimates. Test length, viewed as waiting time on fault coverage, is analyzed next. We derive expressions for its pmf and its probability generating function (pgf). This allows computation of all the higher order moments. In particular, expressions for mean and variance of test length for any specified fault coverage are derived. This is a considerable enhancement of the state of the art in techniques for predicting test length as a function of fault coverage. It is shown that any moment of test length requires knowledge of all the moments of fault coverage, and hence, its pmf. For this reason, expressions for approximating its expected value and variance, for user specified error bounds, are also given. A methodology based on these results is outlined. Experiments carried out on several circuits demonstrate that this technique is capable of providing excellent predictions of test length. Furthermore it is shown, as with fault coverage prediction, that estimates of variances can be used to bound average test length quite effectively.

关键词： fault coverage TEST LENGTH URN MODELS OCCUPANCY WAITING TIME

来源：评论

学校读者我要写书评

暂无评论

fault coverage and defect level estimation models for partially testable MCMs

引用

IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS 2000年第2期147卷 119-124页

作者： Tseng, WD Wang, K Natl Chiao Tung Univ Dept Comp & Informat Sci Hsinchu 30050 Taiwan

The authors propose a simple and efficient mathematical model for designers to estimate fault coverage for partially testable multichip modules (MCMs). This model shows a relation between fault covet-age, lest methodology, and the fraction and distribution of design for testability (DFT) dies in MCMs. Experimental results show that the proposed model can efficiently predict the fault coverage of a partially testable MCM with less than 5% deviation. An automatic DFT dies deployment algorithm, based on the genetic algorithm and the model is proposed to help designers to obtain a fault coverage as close to the upper bound of fault coverage as possible. Two defect level estimation models, which relate fault coverage and manufacturing yield for measuring the test quality of MCMs under equiprobable and non-equiprobable faults, respectively, are also formulated and analysed to support the effectiveness of the model.

关键词： Defect level Mathematical Model fault coverage

来源：评论

学校读者我要写书评

暂无评论

fault coverage on RF VCOs and BIST for Wafer Sort Using Peak-to-Peak Voltage Detectors

引用

JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS 2010年第3期26卷 355-365页

作者： Testa, Luca Lapuyade, Herve Deval, Yann Carbonero, Jean-Louis Begueret, Jean-Baptiste Univ Bordeaux IMS Lab IC Design Team Bordeaux France STMicroelectronics Crolles France

A complete study of the fault coverage achievable on two Radio Frequency (RF) Voltage Controlled Oscillators (VCO) is carried out. The peak-to-peak output voltage detection grants the maximal catastrophic and parametric fault coverage. The VCOs and the BIST (Built-In Self-Test) circuitry are designed using the STM CMOS 65 nm process. The frequency of oscillation is 3.6 GHz and the phase noise obtained at 1 MHz offset from the carrier is of -121.7 dBc/Hz for VCO1 and of -118.8 dBc/Hz for VCO2. The performances of the VCOs are simulated before and after the insertion of the circuitry for the BIST, in order to confirm the transparency of the BIST.

关键词： BIST fault coverage Peak-to-peak voltage detector VCO RF

来源：评论

学校读者我要写书评

暂无评论

fault coverage modeling in nonlinear dynamical systems

引用

AUTOMATICA 2012年第7期48卷 1372-1379页

作者： Mueller, Matthias A. Dominguez-Garcia, Alejandro D. Univ Stuttgart Inst Syst Theory & Automat Control D-70550 Stuttgart Germany Univ Illinois Dept Elect & Comp Engn Urbana IL 61801 USA

In this paper, we propose an approach for modeling fault coverage in nonlinear dynamical systems. fault coverage gives a measure of the likelihood that a system will be able to recover after a fault occurrence. In our setup, the system dynamics are described by a standard state-space model. The system input (disturbance) is considered to be unknown but bounded at all times. Before any fault occurrence, the vector field governing the system dynamics is such that, for any possible input signal, the corresponding system reach set is contained in some region of the state space defined by the system performance requirements. When a fault occurs, the vector field that governs the system dynamics might be altered. fault coverage is defined as the probability that, given a fault has occurred, the system trajectories remain, at all times, within the region of the state-space defined by the performance requirements. Input-to-state stability (ISS) concepts are used to compute estimates of the proposed coverage model. Several examples are discussed in order to illustrate the proposed modeling approach. (C) 2012 Elsevier Ltd. All rights reserved.

关键词： fault coverage fault tolerance Nonlinear systems Invariant sets Input-to-state stability (ISS)

来源：评论

学校读者我要写书评

暂无评论

fault coverage Analysis of Peak-Detector Based BIST for RF LNAs

引用

JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS 2010年第1期26卷 37-45页

作者： Ayadi, R. M. Masmoudi, M. Natl Engn Sch Sfax ENIS Elect Microtechnol & Commun Reach Grp Sfax Tunisia

Analog and mixed-signal testing is becoming an important issue that affects both the time-to-market and the product cost of many SoCs. In order to provide an efficient testing method for 865-870 MHz low noise amplifiers (LNAs), which constitute a mixed-signal circuit, a novel BIST method is developed. This BIST can be easily implemented with a RF peak detector and two comparators. The circuit used in the test and the LNA are designed using 0.35 mu m CMOS technology. The simulation results show higher fault coverage than that of previous test methods. A total of twenty eight short and open (catastrophic) faults and eleven variation parameters have been introduced into the LNA, giving fault coverage of 100% for catastrophic faults and parametric variation. Thus, it provides an efficient structural test, which is suitable for a production test in terms of an area overhead, a test accessibility, and test time.

关键词： Built-in self test (BIST) Low noise amplifiers (LNA) fault model fault coverage

来源：评论

学校读者我要写书评

暂无评论

fault coverage of Constrained Random Test Selection for access control: A formal analysis

引用

JOURNAL OF SYSTEMS AND SOFTWARE 2010年第12期83卷 2607-2617页

作者： Masood, Ammar Ghafoor, Arif Mathur, Aditya P. Air Univ Inst Avion & Aeronaut Avion Engg Dept Islamabad Pakistan Purdue Univ Sch ECE W Lafayette IN 47906 USA Purdue Univ Dept Comp Sci W Lafayette IN 47906 USA

A probabilistic model of fault coverage is presented. This model is used to analyze the variation in the fault detection effectiveness associated with the use of two test selection strategies: heuristics-based and Constrained Random Test Selection (CRTS). These strategies arise in the context of conformance test suite generation for Role Based Access Control (RBAC) systems. The proposed model utilizes coverage matrix based approach for fault coverage analysis. First, two boundary instances of fault distribution are considered and then generalized. The fault coverages of the test suites generated using the heuristics-based and the CRTS strategies, applied to a sample RBAC policy, are then compared through simulation. Finally the simulation results are correlated with a case study. (C) 2010 Elsevier Inc. All rights reserved.

关键词： Role Based Access Control (RBAC) Finite state models W-method fault coverage

来源：评论

学校读者我要写书评

暂无评论

fault coverage of a Timing and Control Flow Checker for Hard Real-Time Systems

Fault Coverage of a Timing and Control Flow Checker for Hard...

引用

IEEE 18th International On-Line Testing Symposium (IOLTS)

作者： Wolf, Julian Fechner, Bernhard Ungerer, Theo Univ Augsburg Augsburg Germany

ISBN: (纸本)9781467320849;9781467320856

Dependability is a crucial requirement of today's embedded systems. To achieve a higher level of fault tolerance, it is necessary to develop and integrate mechanisms for a reliable fault detection. In the context of hard real-time computing, such a mechanism should also guarantee correct timing behavior, an essential requirement for these systems. In this paper, we present results of the fault coverage of a lightweight timing and control flow checker for hard real-time systems. An experimental evaluation shows that more than 30% of injected faults can be detected by our technique, while the number of errors leading to an endless loop is reduced by around 80%. The check mechanism causes only very low overhead concerning additional memory usage (15.0% on average) and execution time (12.2% on average).

关键词： fault coverage hard real-time system fault tolerance checker Defect detection execution time Endless Loop

来源：评论

学校读者我要写书评

暂无评论

fault coverage of a long random test sequence estimated from a short simulation

Fault coverage of a long random test sequence estimated from...

引用

15th IEEE VLSI Test Symposium

作者： Prepin, V David, R Lab d'Automatique de Grenoble (INPG - CNRS - UJF) St-Martin-d'Heres France

ISBN: (纸本)0818678100

Forecasting the fault coverage of a long random test sequence from the results obtained from the simulation of a short test sequence looks like an inaccessible dream. As a matter of fact, a short test sequence detects mainly easy to detect faults, while the test length required for a fault coverage close to 1 depends mainly (almost only) on the most difficult faults. A new 2-parameter model, linking the fault coverage to the test length, was proposed recently [1]. Although these parameters are very difficult to obtain, they can be roughly estimated from a relatively short simulation. According to a previous comment, the results can not be accurate. However they are more accurate that ones obtained from other models proposed in the literature.

关键词： random testing fault coverage test length testability measure short simulation combinational circuits

来源：评论

学校读者我要写书评

暂无评论

On comparing functional fault coverage and defect coverage for memory testing

引用

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1999年第11期18卷 1676-1683页

作者： Kim, VK Chen, T Sun Microelect Palo Alto CA 94303 USA Colorado State Univ Dept Elect Engn Ft Collins CO 80523 USA

The manufacturing of high-quality and reliable semiconductor memories is very important. Many memory testing algorithms have been proposed to improve the quality of semiconductor memories by screening out different memory functional faults. However, the relationships between memory function fault types and the types of defects which cause the functional faults are not well understood. Therefore, the effectiveness of memory testing algorithms based on the functional fault models cannot be realistically determined. This paper evaluates the effectiveness of the memory testing algorithms based on the defect coverage by comparing the defect coverage of known memory testing algorithms and the functional fault coverage of the same testing algorithms using the same defect statistics. The experimental results show that the differences among the defect coverage of the 11 memory testing algorithms other than checkerboard and sliding diagonal tests were not significant as previously believed using memory functional fault coverage as the coverage metric.

关键词： defect coverage defect coverage estimation effectiveness of memory tests fault coverage memory testing memory testing algorithms

来源：评论

学校读者我要写书评

暂无评论

Power-Aware Testing for Maximum fault coverage in Analog and Digital Circuits Simultaneously

引用

IETE TECHNICAL REVIEW 2022年第6期39卷 1395-1409页

作者： Singh, Vivek Kumar Sarkar, Trupa Pradhan, Sambhu Nath Natl Inst Technol Agartala ECE Dept Agartala India

In this paper, a method for maximum fault coverage with minimum power dissipation, during the testing of analog and digital circuits of mixed-signal System-on-Chip (SOC) simultaneously using Genetic Algorithm, (GA) is proposed. Mixed-signal SOC consists mainly of an analog block, a digital block and a DAC/ADC (Digital to Analog Converter/Analog to Digital Converter). Due to the presence of analog and digital circuits in mixed-signal SOCs, the testing procedure is difficult from that of only analog or digital circuit testing. Here stuck at 0/1 faults are considered for digital circuits, and stuck open/short faults are considered for analog circuits. In analog testing fault modeling, fault injection and fault simulation are done. The outputs of the analog block and some independent digital signals are given to the digital block. The GA-based approach is used for power-aware ordering of test patterns considering pattern dependency on previous patterns at the input of digital block as input patterns. The effect of noise on analog test signals has also been investigated here with the area analysis of the circuit. An average of 92.43% fault coverage and 13.56% maximum power saving is achieved when this methodology is applied to ITC 97 (Analog block) and ISCAS 85 (Digital block) benchmark circuits, respectively. A trade-off between fault coverage and power dissipation has been presented.

关键词： ADC fault coverage Genetic Algorithm (GA) mixed-signal Operational Amplifier (Op-Amp) power dissipation SOC

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：