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IEEE DESIGN & TEST 2023年第2期40卷 8-58页

作者： Su, Fei Liu, Chunsheng Stratigopoulos, Haralampos-G. Intel Corp Folsom CA 95630 USA Alibaba Inc Sunnyvale CA 94085 USA Sorbonne Univ LIP6 Lab CNRS F-75005 Paris France

Editor 's notes:Hardware realization of artificial intelligence (AI) requires new design styles and even underlying technologies than those used in traditional digital processors or logic circuits. Therefore, their dependability and testability requirements, challenges, and solutions are fundamentally different and unique. This survey article covers this very important topic and provides insight to such issues.-Mehdi Tahoori, Karlsruhe Institute of Technology

关键词： Neurons Artificial intelligence Biological neural networks Synapses Computer architecture Hardware acceleration Computational modeling AI hardware accelerators neuromorphic computing artificial neural networks spiking neural networks fault modeling and simulation testability dependability fault tolerance functional safety

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Radiation-Induced fault simulation of SOI/SOS CMOS LSI's Using Universal Rad-SPICE MOSFET Model

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JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS 2017年第1期33卷 37-51页

作者： Petrosyants, Konstantin O. Sambursky, Lev M. Kharitonov, Igor A. Lvov, Boris G. Natl Res Univ Higher Sch Econ Dept Elect Engn Moscow Inst Elect & Math Moscow Russia Russian Acad Sci Dept Analog Circuits Design Automat Inst Design Problems Microelect Moscow Russia

The methodology of modeling and simulation of environmentally induced faults in radiation hardened SOI/SOS CMOS IC's is presented. It is realized at three levels: CMOS devices - typical analog or digital circuit fragments - complete IC's. For this purpose, a universal compact SOI/SOS MOSFET model for SPICE simulation software with account for TID, dose rate and single event effects is developed. The model parameters extraction procedure is described in great depth taking into consideration radiation effects and peculiarities of novel radiation-hardened (RH) SOI/SOS MOS structures. Examples of radiation-induced fault simulation in analog and digital SOI/SOS CMOS LSI's are presented for different types of radiation influence. The simulation results show the difference with experimental data not larger than 10-20% for all types of radiation.

关键词： SOI CMOS circuits fault modeling and simulation Radiation hardness TID Dose rate Single events Compact SPICE models Novel RH SOI MOS structures Model parameter extraction

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Performance model-based reliability simulation analysis of multi-state electromechanical system

Performance model-based reliability simulation analysis of m...

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Prognostics and System Health Management Conference (PHM-Chongqing)

作者： Hu, Yubin Wang, Ruping Wang, Xin Wang, Tao Zhan, Zitao AVIC China Aeropolytechnol Estab Design & Anal Dept Beijing Peoples R China AQSIQ Key Lab Qual Infrastruct Efficacy Res Beijing Peoples R China

ISBN: (纸本)9781538653807

Base on the research on common methods of reliability modeling for multi-state system, performance model-based technique, which overcoming the shortages of the existing methods, is proposed to solve reliability analysis and evaluation for complex electromechanical system with multi-state fault features in this paper. The main idea about this technology can be demonstrated as follows. The components fault modeling need to be finished based on the system performance model at first, by describing the continuous variation of performance parameters to simulate the process of components degradation from the normal to the complete failure. Then, components fault injecting to the performance model also need to be used to analyze the response of system under fault state. At last, system reliability evaluation could be achieved depending on the first two steps. This paper takes the fuel pump as a case study, and the results show that performance model-based reliability simulation technique is suitable for the reliability evaluation of typical electromechanical systems in most aviation equipments.

关键词： Performance model fault modeling and simulation multi-state Monte-Carlo system reliability analysis fuel pump

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Heaping of Sorrow Upon Sorrow 4

Heaping of Sorrow Upon Sorrow

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4th IEEE International Symposium on Smart Electronic Systems (ISES)

作者： Bhowmik, Biswajit Indian Inst Informat Technol Design & Mfg Dept Comp Sci & Engn Kurnool 518007 Andhra Pradesh India

ISBN: (纸本)9781538691724

With the continuous dimension shrinkage, the communication channels of networks-on-chip (NoCs) are often vulnerable to many logic level manufacturing faults resulting in miscellaneous system-level failures. Correspondingly, their effects on the system performance are widely visible. A new distributed, online, test solution that addresses stuck-at and open faults in NoC channels in view of maintaining system reliability and yield, is presented here. Considering a suitable test scheduling scheme, the test time and associated performance overhead are lowered. The evaluation of the proposed scheme on a 3x3 mesh NoC details its runtime performance. It is observed that the proposed solution saves up to 125% test time. Further, average packet latency is improved by 31.93% while energy consumption is reduced by 27.88%.

关键词： multiprocessor and multi-core architectures high performance computing and communication fault-tolerance reliability and yield fault modeling and simulation on-line system performance evaluation

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fault simulation in Radiation-Hardened SOI CMOS VLSIs using Universal Compact MOSFET Model 17

Fault Simulation in Radiation-Hardened SOI CMOS VLSIs using ...

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17th IEEE Latin-American Test Symposium (LATS)

作者： Petrosyants, Konstantin O. Sambursky, Lev M. Kharitonov, Igor A. Lvov, Boris G. Natl Res Univ Higher Sch Econ Moscow Inst Elect & Math Dept Elect Engn Moscow Russia Russian Acad Sci Inst Design Problems Microelect Dept Analog Circuits Design Automat Moscow Russia

ISBN: (纸本)9781509013319

The methodology of modeling and simulation of environmentally induced faults in radiation hardened SOI CMOS ICs is presented. For this purpose, the universal compact SPICE SOI MOSFET model with account for TID, dose rate and single event effects is used. First, the model parameters extraction procedure is described in more details taking into consideration radiation effects and peculiarities of novel radiation-hardened (RH) SOI MOS structures. The results of analog and digital SOI CMOS circuits simulation show the difference with experimental data not more than 10-20% for all types of radiation.

关键词： SOI CMOS circuits fault modeling and simulation radiation hardness TID dose rate single events compact SPICE models novel RH SOI MOS structures model parameter extraction

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Layout-Oriented Defect Set Reduction for Fast Circuit simulation in Cell-Aware Test 25

Layout-Oriented Defect Set Reduction for Fast Circuit Simula...

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25th IEEE Asian Test Symposium (ATS)

作者： Liu, Hsuan-Wei Lin, Bing-Yang Wu, Cheng-Wen Natl Tsing Hua Univ Dept Elect Engn Hsinchu 30013 Taiwan

ISBN: (纸本)9781509038091

The cell-aware test (CAT) methodology was previously proposed to target cell-internal faults that cannot be easily detected by gate-level stuck-at fault (SAF) patterns generated by conventional ATPG. It was shown to reduce the defect level on CMOS-based designs, with the help of detailed defect injected transistor-level circuit simulation and defect-enhanced SAF ATPG. The detailed transistor-level circuit simulation has been considered an issue in CAT, as it is very time consuming. The problem mainly lies in that all parasitic capacitors and resistors extracted from cell layout are considered as defect targets, so the defect set is large. To reduce the defect set, and therefore the circuit simulation time, we take layout into consideration when we construct the defect set for each cell, effectively removing the redundant or unnecessary defects and therefore reducing the circuit simulation time dramatically. We propose a generalized approach that can be used to build the fault models based on the cell layout, where the generated faults are closer to the realistic physical defects on the layout, so the number of faults is significantly reduced. The proposed method is verified by commercial 180nm and 350nm CMOS standard cell library, and the circuit simulation time is reduced to only 19% or even lower as compared with the original CAT methodology.

关键词： Automatic test pattern generation (ATPG) cell-aware test (CAT) circuit simulation defect-based testing fault modeling and simulation

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Rapid transient fault insertion in large digital systems

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MICROPROCESSORS AND MICROSYSTEMS 2013年第2期37卷 147-154页

作者： Rohani, Alireza Kerkhoff, Hans G. Univ Twente CTIT Testable Design & Test Integrated Syst Grp NL-7500 AE Enschede Netherlands

This paper presents a technique for rapid transient fault injection, regarding the CPU time, to perform simulation-based fault-injection in complex System-on-Chip Systems (SoCs). The proposed approach can be applied to complex circuits, as it is not required to modify the top-level modules of a design;moreover, it is capable to inject a wide range of fault models in a design and finally a competitive reduction in terms of CPU time will be achieved. The root of our method is based on the usage of simulator-commands along with partial code modification techniques. To prove the efficiency of the proposed method, it has been implemented on two case studies, a pre-synthesized netlist of an AVR microcontroller from ATMEL and a post placed-and-routed Verilog netlist of a high performance reconfigurable processor in 90-nm UMC technology, Xentium processor from Recore Systems. Experimental results show that our technique is able to reduce the CPU time by a factor ranging from 27% to 67% compared with typical simulation-based fault-injection approaches and by a factor of 10% compared with rapid simulation-based techniques. (C) 2012 Elsevier B.V. All rights reserved.

关键词： Component Failure analysis fault modeling and simulation Transient faults

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Study of the effects of SEU-induced faults on a pipeline-protected microprocessor

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IEEE TRANSACTIONS ON COMPUTERS 2007年第12期56卷 1585-1596页

作者： Touloupis, Emmanuel Flint, James A. Chouliaras, Vassilios A. Ward, David D. InAccess Networks SA Microelect Grp Athens 15125 Greece Univ Loughborough Dept Elect & Elect Engn Loughborough LE11 3TU Leics England MIRA Ltd Elect Grp Nuneaton CV10 0TU Warwick England

This paper presents a detailed analysis of the behavior of a novel fault-tolerant 32-bit embedded CPU as compared to a default (non-fault-tolerant) implementation of the same processor during a fault injection campaign of single and double faults. The fault-tolerant processor tested is characterized by per-cycle voting of microarchitectural and the flop-based architectural states, redundancy at the pipeline level, and a distributed voting scheme. Its fault-tolerant behavior is characterized for three different workloads from the automotive application domain. The study proposes statistical methods for both the single and dual fault injection campaigns and demonstrates the fault-tolerant capability of both processors in terms of fault latencies, the probability of fault manifestation, and the behavior of latent faults.

关键词： fault injection fault modeling and simulation SEU soft error microprocessor test fault tolerance

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LAYOUT-LEVEL TECHNIQUES FOR TESTABILITY IMPROVEMENT OF MOS PHYSICAL DESIGNS

LAYOUT-LEVEL TECHNIQUES FOR TESTABILITY IMPROVEMENT OF MOS P...

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6TH MEDITERRANEAN ELECTROTECHNICAL CONF ( MELECON 91 )

作者： SANTOS, MB GONCALVES, FM SOUSA, JJT TEIXEIRA, JP

ISBN: (纸本)0879426551

A methodology for physical testability assessment is reviewed, and a technique to enhance the physical testability of ICs with BIST (built-in self test) is presented. It is shown that an appropriate choice of a primitive polynomial can improve the realistic fault coverage, obtained with pseudo-random test patterns or, conversely, can lead to reduced test lengths, for the same fault coverage. The results are ascertained by the physical design and (linear feedback shift register specification of a self-test ALU (arithmetic logic unit).

关键词： fault modeling and simulation TESTABILITY ANALYSIS CMOS BIST

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