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Hardware compiler realising concurrent processes in reconfigurable logic

IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES 2001年第4-5期148卷 152-162页

作者： Diessel, O Milne, G Univ New S Wales Sch Comp Sci & Engn Sydney NSW 2052 Australia Univ Western Australia Dept Comp Sci & Software Engn Crawley WA 6009 Australia

Reconfigurable computers based on field programmable gate array technology allow applications to be realised directly in digital logic. The inherent concurrency of hardware distinguishes such computers from microprocessor-based machines in which the concurrency of the underlying hardware is fixed and abstracted from the programmer by the software model. However, reconfigurable logic provides us with the potential to exploit 'real' concurrency. It is therefore interesting to know how to exploit this concurrency, how to model concurrent computations, and which languages allow this dynamic hardware to be programmed most effectively. The purpose of this work is to describe an FPGA compiler for the Circal process algebra. In so doing, the authors demonstrate that behavioural descriptions expressed in a process algebraic language can be readily and intuitively compiled to reconfigurable logic and that this contributes to the goal of discovering appropriate high-level languages for run-time reconfiguration.

关键词： digital logic Formal languages and computational linguistics Circal process algebra Parallel architecture formal languages reconfigurable logic Logic and switching circuits behavioural descriptions Parallel programming and algorithm theory microprocessor-based machines process algebraic language high-level languages hardware compiler dynamic hardware Digital circuit design, modelling and testing concurrent computation modelling Logic circuits parallel architectures Computer-aided circuit analysis and design reconfigurable computers field programmable gate arrays Computer-aided logic design run-time reconfiguration concurrent processes Electronic engineering computing reconfigurable architectures concurrency theory process algebra field programmable gate array technology real concurrency logic CAD FPGA compiler software model circuit layout CAD

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FPGA Implementation of a Unidirectional Systolic array Generator for Matrix-Vector Multiplication

FPGA Implementation of a Unidirectional Systolic Array Gener...

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IEEE International Conference on Signal Processing and Communications

作者： Karra, M. Ch. Bekakos, M. P. Milovanovic, I. Z. Milovanovic, E. I. Democritus Univ Thrace Lab Digital Syst Dept Elect & Comp Engn Sch Engn GR-67100 Xanthi Greece Fac Elect Engn Belgrade 18000 Serbia

ISBN: (纸本)9781424412358

Systolic arrays may prove ideal structures for the representation and the mapping of many applications concerning various numerical and non-numerical scientific applications. Especially, some formulation of Dynamic Programming (DP) - a commonly used technique for solving a wide variety of discrete optimization problems, such as scheduling, string-editing, packaging, and inventory management-can be solved in parallel on systolic arrays as matrix-vector products. Systolic arrays usually have a very high rate of I/O and are well suited for intensive parallel operations Herein is a description of the FPGA hardware implementation of a matrix-vector multiplication algorithm designed to produce a unidirectional systolic array representation.

关键词： Systolic arrays parallel algorithm field programmable gate array technology

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A Hybrid Genetic-Programming Swarm-Optimisation Approach for Examining the Nature and Stability of High Frequency Trading Strategies 13

A Hybrid Genetic-Programming Swarm-Optimisation Approach for...

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13th International Conference on Machine Learning and Applications (ICMLA)

作者： Funie, Andreea-Ingrid Salmon, Mark Luk, Wayne Imperial Coll London Dept Comp London SW7 2AZ England Univ Cambridge Fac Econ Cambridge CB3 9DD England

ISBN: (纸本)9781479974153

Advances in high frequency trading in financial markets have exceeded the ability of regulators to monitor market stability, creating the need for tools that go beyond market microstructure theory and examine markets in real time, driven by algorithms, as employed in practice. This paper investigates the design, performance and stability of high frequency trading rules using a hybrid evolutionary algorithm based on genetic programming, with particle swarm optimisation layered on top to improve the genetic operators' performance. Our algorithm learns relevant trading signal information using Foreign Exchange market data. Execution time is significantly reduced by implementing computationally intensive tasks using field programmable gate array technology. This approach is shown to provide a reliable platform for examining the stability and nature of optimal trading strategies under different market conditions through robust statistical results on the optimal rules' performance and their economic value.

关键词： economics field programmable gate arrays foreign exchange trading genetic algorithms particle swarm optimisation economic value field programmable gate array technology financial markets foreign exchange market data genetic programming high frequency trading strategies hybrid evolutionary algorithm monitor market stability Algorithm design and analysis Genetics Noise Prediction algorithms Sociology Statistics Testing Genetic Algorithm (GA) Particle swarm optimization field programmable gate arrays Algorithm design and analysis Prediction algorithms economic value Sociology evolutionary algorithm Genetics economics Noise Stock exchanges Exchange rates design performance

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Reusable IP Cores Library for EV Propulsion Systems

Reusable IP Cores Library for EV Propulsion Systems

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IEEE International Symposium on Industrial Electronics (ISIE)

作者： de Castro, Ricardo Araujo, Rui Esteves Feitas, Diamantino Univ Porto Fac Engn Oporto Portugal

ISBN: (纸本)9781424463916

This paper presents a new control chip design, based on field programmable gate array (FPGA) technology, for multi-motor electric vehicles. The control chip builds around a reusable intellectual property (IP) core, named Propulsion Control System (PCS);which features motor control functions with field orientation methods, and energy loss minimization of induction motors. To reduce the cost, implementation issues related with the limited number of dedicated multipliers were overcome using an efficient computational block, based on resource sharing strategy. Due to the parallel processing offered by FPGAs, the resulting implementation can be effortlessly adapted to different electric vehicles topologies, like single or multi-motor drive. As proof of concept, two prototypes with single and multi-motor configurations were developed with the control chip design implemented in a low cost Xilinx Spartan 3 FPGA. Experimental verification of the energy loss minimization algorithm is provided, showing considerable energy savings (>15%) in low speed conditions and improving the electric vehicle range per charge.

关键词： EV propulsion systems Xilinx Spartan 3 FPGA control chip design electric vehicles energy loss minimization field orientation methods field programmable gate array technology field programmable gate arrays induction motor drives induction motors industrial property intellectual property machine vector control motor control functions multimotor drive multimotor electric vehicles parallel processing propulsion propulsion control system resource sharing strategy reusable IP cores library

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