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ENGINEERING REPORTS 2025年第1期7卷

作者： Deng, Quan Liu, Qiang Tianjin Univ Sch Microelect Tianjin Peoples R China Tianjin Key Lab Imaging & Sensing Microelect Techn Tianjin Peoples R China

Molecular dynamics simulation is a common method to help humans understand the microscopic world. The traditional general-purpose high-performance computing platforms are hindered by low computational and power efficiency, constraining the practical application of large-scale and long-time many-body molecular dynamics simulations. In order to address these problems, a novel molecular dynamics accelerator for the Tersoff potential is designed based on field-programmable gate array (FPGA) platforms, which enables the acceleration of LAMMPS using FPGAs. Firstly, an on-the-fly method is proposed to build neighbor lists and reduce storage usage. Besides, multilevel parallelizations are implemented to enable the accelerator to be flexibly deployed on FPGAs of different scales and achieve good performance. Finally, mathematical models of the accelerator are built, and a method for using the models to determine the optimal-performance parameters is proposed. Experimental results show that, when tested on the Xilinx Alveo U200, the proposed accelerator achieves a performance of 9.51 ns/day for the Tersoff simulation in a 55,296-atom system, which is a 2.00x$$ \times $$ increase in performance when compared to Intel I7-8700K and 1.70x$$ \times $$ to NVIDIA Tesla K40c under the same test case. In addition, in terms of computational efficiency and power efficiency, the proposed accelerator achieves improvements of 2.00x$$ \times $$ and 7.19x$$ \times $$ compared to Intel I7-8700K, and 4.33x$$ \times $$ and 2.11x$$ \times $$ compared to NVIDIA Titan Xp, respectively.

关键词： field-programmable gate array high-performance computing molecular dynamics reconfigurable computing Tersoff potential

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field-programmable gate array implementation of a single photoncounting receive modem 36

Field-programmable gate array implementation of a single pho...

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Conference on Free-Space Laser Communications XXXVI

作者： Simon, William P. Downey, Jennifer N. Lantz, Nicholas C. Bizon, Thomas P. Marsden, Michael A. Vyhnalek, Brian E. Zeleznikar, Daniel J. NASA Glenn Res Ctr 21000 Brookpk Rd Cleveland OH 44135 USA

ISBN: (纸本)9781510670150;9781510670143

We present a field-programmable gate array (FPGA) implementation of a single photon-counting receive modem for a pulse position modulated signal. The modem is compliant with the Consultative Committee for Space Data Systems (CCSDS) High Photon Efficiency (HPE) Optical Communications Coding and Synchronization standard and is capable of a maximum data rate of 267 Mbps. The system is designed on a commercial off-the-shelf FPGA platform and utilizes superconducting nanowire single photon counting detectors, analog to digital converters (ADCs) to sample the detectors, and two FPGAs. Symbol timing recovery, photon counting, convolutional deinterleaving, and codeword synchronization are performed in the first FPGA. The second FPGA performs iterative decoding on each codeword of the serially concatenated pulse position modulated (SCPPM) signal. A digital filter is included to compensate for timing jitter of the detector, and the decoder throughput can be adjusted through reconfigurable parallelization. The decoder also implements a resource-efficient, algorithmic polynomial interleaver and deinterleaver. Both FPGAs can be reconfigured to switch between pulse position modulation (PPM)-16 and PPM-32 with code rates 1/3, 1/2, and 2/3. In this paper, we describe the receiver architecture and FPGA implementation of the timing recovery loop and SCPPM decoder, FPGA utilization for the different modes, and receive modem characterization test results.

关键词： field-programmable gate array optical receiver timing recovery iterative decoder

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Parallelized field-programmable gate array Data Processing for High-Throughput Pulsed-Radar Systems

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SENSORS 2025年第1期25卷 239页

作者： Pitcher, Aaron D. Georgiev, Mihail Nikolova, Natalia K. Nicolici, Nicola McMaster Univ Electromagnet Vis EMVi Res Lab Hamilton ON L8S 4L8 Canada McMaster Univ Comp Aided Design & Test CADT Res Grp Hamilton ON L8S 4L8 Canada

A parallelized field-programmable gate array (FPGA) architecture is proposed to realize an ultra-fast, compact, and low-cost dual-channel ultra-wideband (UWB) pulsed-radar system. This approach resolves the main shortcoming of current FPGA-based radars, namely their low processing throughput, which leads to a significant loss of data provided by the radar receiver. The architecture is integrated with an in-house UWB pulsed radar operating at a sampling rate of 20 gigasamples per second (GSa/s). It is demonstrated that the FPGA data-processing speed matches that of the radar output, thus eliminating data loss. The radar system achieves a remarkable speed of over 9000 waveforms per second on each channel. The proposed architecture is scalable to accommodate higher sampling rates and various waveform periods. It is also multi-functional since the FPGA controls and synchronizes two transmitters and a dual-channel receiver, performs signal reconstruction on both channels simultaneously, and carries out user-defined averaging, trace windowing, and interference suppression for improving the receiver's signal-to-noise ratio. We also investigate the throughput rate while offloading radar data onto an external device through an Ethernet link. Since the radar data rate significantly exceeds the Ethernet link capacity, we show how the FPGA-based averaging and windowing functions are leveraged to reduce the amount of offloaded data while fully utilizing the radar output.

关键词： concealed weapon detection field-programmable gate array equivalent-time sampling subsampling ultra-wideband measurement techniques ultra-wideband radar

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field-programmable gate array (FPGA) hardware design and implementation of a new area efficient elliptic curve crypto-processor

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TURKISH JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES 2021年第4期29卷 2127-2139页

作者： Kashif, Muhammad Cicek, Ihsan Istanbul Sehir Univ Dept Elect Engn Istanbul Turkey Istinye Univ Dept Elect Engn Istanbul Turkey

Elliptic curve cryptography provides a widely recognized secure environment for information exchange in resource-constrained embedded system applications, such as Internet-of-Things, wireless sensor networks, and radio frequency identification. As the elliptic-curve cryptography (ECC) arithmetic is computationally very complex, there is a need for dedicated hardware for efficient computation of the ECC algorithm in which scalar point multiplication is the performance bottleneck. In this work, we present an ECC accelerator that computes the scalar point multiplication for the NIST recommended elliptic curves over Galois binary fields by using a polynomial basis. We used the Montgomery algorithm with projective coordinates for the scalar point multiplication. We designed a hybrid finite field multiplier based on the standard Karatsuba and shift-and-add multiplication algorithms that achieve one finite field multiplication in m2 clock cycles for a key-length of m. The proposed design has been modeled in Verilog hardware description language (HDL), functionally verified with simulations, and implemented for field-programmable gate array (FPGA) devices using vendor tools to demonstrate hardware efficiency. Finally, we have integrated the ECC accelerator as an AXI4 peripheral with a synthesizable microprocessor on an FPGA device to create an elliptic curve crypto-processor.

关键词： Elliptic curve cryptography Karatsuba multiplier crypto-accelerator crypto-processor scalar multiplica-tion field-programmable gate array

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Embedded linear model predictive control in field-programmable gate array using register-transfer level implementation and floating-point representation applied to a quadrotor system model

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PROCEEDINGS OF THE INSTITUTION OF MECHANICAL ENGINEERS PART I-JOURNAL OF SYSTEMS AND CONTROL ENGINEERING 2022年第2期236卷 370-381页

作者： Castanheira de Farias, Alceu Bernardes Murilo, Andre Lopes, Renato Vilela Univ Brasilia Fac Technol Dept Mech Engn Campus Univ Darcy Ribeiro BR-70910900 Brasilia DF Brazil Univ Brasilia Fac Gama Area Especial Ind Projecao A Setor Leste Brasilia DF Brazil

Model predictive control is increasingly becoming a popular control strategy for a wide range of applications in both industry and academia, mainly motivated by its ability to systematically handle constraints imposed on a system, regardless of its nature. However, this generates high computational demands, limiting the applicability of model predictive control. field-programmable gate arrays are reconfigurable hardware platforms that allow the parallel implementation of model predictive control, accelerating such algorithms, but most works found in the literature opt to use high-level synthesis tools and fixed-point numeric representation to generate embedded controllers, resulting in faster-designed solutions but not exactly efficient and flexible ones, that can be applied to different scenarios. Regarding such matter, this work proposes the manual implementation (register-transfer level implementation) of linear model predictive control and the usage of floating-point numeric representation applied to a quadrotor system. The initial results obtained using the proposed controller are presented in this article, achieving 29.34 ms of calculation time at 50 MHz for the attitude control of a quadrotor model containing twelve states and four control outputs.

关键词： Control systems embedded systems model predictive control field-programmable gate array quadrotor

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field-programmable gate array Implementation of a Single Photon-Counting Receive Modem

Field-Programmable Gate Array Implementation of a Single Pho...

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作者： Brian E Vyhnalek Jennifer N Downey Daniel J Zeleznikar Nicholas C Lantz Michael A Marsden William P Simon Thomas P Bizon

modulation (PPM)-16 and PPM-32 with code rates 1/3, 1/2, and 2/3. In this paper, we describe the receiver

关键词： field-programmable gate array Pulse Position Modulation Decoding Concatenated Codes Timing Recovery Optical Receiver Iterative decoder

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High-speed and area-efficient Sobel edge detector on field-programmable gate array for artificial intelligence and machine learning applications

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COMPUTATIONAL INTELLIGENCE 2021年第3期37卷 1056-1067页

作者： Sikka, Prateek Asati, Abhijit R. Shekhar, Chandra Birla Inst Technol & Sci Elect & Elect Engn Dept Vidya Vihar Campus Pilani Rajasthan India

Sobel edge detector is an algorithm commonly used in image processing and computer vision to extract edges from input images using derivative of image pixels in x and y directions against surrounding pixels. Most artificial intelligence and machine learning applications require image processing algorithms running in real time on hardware systems like field-programmable gate array (FPGAs). They typically require high throughput to match real-time speeds and since they run alongside other processing algorithms, they are required to be area efficient as well. This article proposes a high-speed and low-area implementation of the Sobel edge detection algorithm. We created the design using a novel high-level synthesis (HLS) design method based on application specific bit widths for intermediate data nodes. Register transfer level code was generated using MATLAB hardware description language (HDL) coder for HLS. The generated HDL code was implemented on Xilinx Kintex 7 field programmable gate array (FPGA) using Xilinx Vivado software. Our implementation results are superior to those obtained for similar implementations using the vendor library block sets as well as those obtained by other researchers using similar implementations in the recent past in terms of area and speed. We tested our algorithm on Kintex 7 using real-time input video with a frame resolution of 1920 x 1080. We also verified the functional simulation results with a golden MATLAB implementation using FPGA in the loop feature of HDL Verifier. In addition, we propose a generic area, speed, and power improvement methodology for different HLS tools and application designs.

关键词： field-programmable gate array hardware description language high-level synthesis MATLAB HDL coder register transfer language Sobel edge detection Vivado

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A field-programmable gate array Implementation of a Cognitive Radar Target Recognition System

A Field-Programmable Gate Array Implementation of a Cognitiv...

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IEEE Radar Conference (RadarConf)

作者： Sessions, Calvin A. Romero, Ric A. Fouts, Douglas J. Naval Postgrad Sch Elect & Comp Engn Monterey CA 93943 USA

ISBN: (纸本)9781728153681

In this paper, we design a field-programmable gate array (FPGA) implementation of a cognitive radar (CRr) target recognition system for electronic warfare applications. This study expands on the closed-loop adaptive matched waveform transmission technique called probability of weighted energy (PWE). This work also investigates the feasibility of applying the PWE technique in a functional digital hardware realization. Initially, a PWE Monte Carlo simulation model is developed in the Verilog hardware description language that is simulated in the Xilinx Vivado environment. The Verilog module components developed in the Monte Carlo model are then incorporated into a CRr target recognition system experiment utilizing the Xilinx VCU118 Evaluation Board. The VCU118 features the Virtex UltraScale+ high-performance FPGA to accomplish CRr adaptive waveform generation and transmission, digital signal processing requirements, and target classification. The Rohde & Schwarz SMW200A Vector Signal Generator and FSW Signal & Spectrum Analyzer function as the radar system transmitter and receiver, respectively, while the FPGA implementation enables the closed feedback loop used by the CRr.

关键词： cognitive radar probability of weighted energy field-programmable gate array target classification eigenwave-form CRr PWE FPGA

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The concept of multicore computing and processing in a field-programmable gate array chip

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Procedia Computer Science 2024年 246卷 2400-2409页

作者： Paweł Poczekajło Łukasz Gołka Robert Suszyński Patryk Widuliński Koszalin University of Technology. ul Śniadeckich 2 75-453 Koszalin Poland

The article concerns the issue of multicore processing and implementation. The topic is introduced considering the functional division of various architectures. Examples of large-scale multicore architectures (with 144 and 1024 computational cores) are also presented. The main goal of the authors is to present the concept of implementing a multicore architecture in a field-programmable gate array (FPGA). An available solution of the Nios II processor from the Intel library in the Quartus environment is presented. Additionally, the authors discuss their own concept of a computational core, outlining key assumptions, advantages and disadvantages, as well as potential issues.

关键词： multicore multicore processing multi-ALU hardware implementation computational core implementation field-programmable gate array FPGA concept

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One Trillion True Random Bits Generated With a field-programmable gate array Actuated Magnetic Tunnel Junction

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IEEE MAGNETICS LETTERS 2024年 15卷 1页

作者： Dubovskiy, Andre Criss, Troy El Valli, Ahmed Sidi Rehm, Laura Kent, Andrew D. Haas, Andrew NYU Dept Phys New York NY 10003 USA

Large quantities of random numbers are crucial in a wide range of applications. We have recently demonstrated that perpendicular nanopillar magnetic tunnel junctions (pMTJs) can produce true random bits when actuated with short pulses. However, our implementation used high-end and expensive electronics, such as a high-bandwidth arbitrary waveform generator and analog-to-digital converter, and was limited to relatively low data rates. Here, we significantly increase the speed of true random-number generation of our stochastic actuated pMTJs (SMART-pMTJs) using field-programmable gate arrays (FPGAs), demonstrating the generation of over ${\text{10}}<^>{\text{12}}$ bits at rates exceeding 10 Mb/s. The resulting bitstreams pass the NIST Statistical Test Suite for randomness with only one xor operation. In addition to a hundred-fold reduction in the setup cost and a thousand-fold increase in bitrate, the advancement includes simplifying and optimizing random bit generation with a custom-designed analog daughterboard to interface an FPGA and SMART-pMTJ. The resulting setup further enables FPGA at-speed processing of MTJ data for stochastic modeling and cryptography.

关键词： field programmable gate arrays Magnetic tunneling Junctions Switches Pulse measurements Voltage measurement Magnetization Spin electronics magnetic tunnel junction field-programmable gate array probabilistic computing p-bits

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