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An Implementation of Multiple-Standard Video Decoder on a Mixed-Grained Reconfigurable Computing Platform

IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS 2016年第5期E99D卷 1285-1295页

作者： Liu, Leibo Wang, Dong Chen, Yingjie Zhu, Min Yin, Shouyi Wei, Shaojun Tsinghua Univ Inst Microelect Beijing 100084 Peoples R China Beijing Jiaotong Univ Inst Informat Sci Beijing Peoples R China

This paper presents the design of a multiple-standard 1080 high definition (HD) video decoder on a mixed-grained reconfigurable computing platform integrating coarse-grained reconfigurable processing units (RPUs) and FPGAs. The proposed RPU, including 16 x 16 multi-functional processing elements (PEs), is used to accelerate compute-intensive tasks in the video decoding. A soft-core-based microprocessor array is implemented on the FPGA and adopted to speed-up the dynamic reconfiguration of the RPU. Furthermore, a mail-box-based communication scheme is utilized to improve the communication efficiency between RPUs and FPGAs. By exploiting dynamic reconfiguration of the RPUs and static reconfiguration of the FPGAs, the proposed platform achieves scalable performances and cost trade-offs to support a variety of video coding standards, including MPEG-2, AVS, H.264, and HEVC. The measured results show that the proposed platform can support H.264 1080 HD video streams at up to 57 frames per second (fps) and HEVC 1080 HD video streams at up to 52fps under 250MHz, at the same time, it achieves a 3.6x performance gain over an industrial coarse-grained reconfigurable processor for H. 264 decoding, and a 6.43x performance boosts over a general purpose processor based implementation for HEVC decoding.

关键词： algorithm mapping coarse-grained reconfigurable array field-programmable gate array reconfigurable computing video decoding

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Development of Compact, Cost-effective, FPGA-Based Data Acquisition System for the iPET System

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JOURNAL OF MEDICAL AND BIOLOGICAL ENGINEERING 2017年第6期37卷 858-866页

作者： Min, Eungi Kim, Kwangdon Lee, Hakjae Kim, Hyun-Il Chung, Yong Hyun Kim, Yongkwon Joung, Jinhun Kim, Kyeong Min Joo, Sung-Kwan Lee, Kisung Korea Univ Dept IT Convergence Seoul South Korea Korea Univ Dept Bioconvergence Engn Seoul South Korea Korea Univ Sch Biomed Engn Seoul South Korea Yonsei Univ Dept Radiat Convergence Engn Wonju South Korea Korea Inst Nucl Safety Daejeon South Korea NuCare Inc Incheon South Korea Korea Inst Radiol & Med Sci Div Med Radiat Equipment Seoul South Korea Korea Univ Sch Elect Engn Seoul South Korea

Positron emission tomography (PET) is a nuclear medicine imaging technology used to analyze physiological processes. An in-beam PET is used to verify the delivered dose during ion-beam therapy. Our group investigates the prototype C-shaped PET system, which is called the iPET system. In this study, we develop an expendability-enhanced field-programmable gate array (FPGA)-based data acquisition system for the iPET. We organize this data acquisition (DAQ) system using only one DAQ board, to ensure a compact and cost-effective DAQ system. We design the FPGA using modular functions, which include synchronization, deserialization, pulse height analysis, and data packaging functions. As a result, energy spectra and well-separated 9 x 9 flood images of the entire detector module are achieved. We obtain reconstructed PET images of point source (4 mm diameter), three cylindrical phantoms (3 cm diameter), and four sphere phantoms (3.0, 2.2, 1.3 and 1.0 cm diameter). We achieve approximately 300 kcps of maximum single count rate. The obtained results prove the compactness and cost-effectiveness of the proposed DAQ system.

关键词： In-beam PET Data acquisition system field-programmable gate array Modular function

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MIPSfpga: using a commercial MIPS soft-core in computer architecture education

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IET CIRCUITS DEVICES & SYSTEMS 2017年第4期11卷 283-291页

作者： Harris, Sarah L. Harris, David M. Chaver, Daniel Owen, Robert Kakakhel, Zubair L. Sedano, Enrique Panchul, Yuri Ableidinger, Bruce Univ Nevada Dept Elect & Comp Engn Las Vegas NV 89154 USA Harvey Mudd Coll Dept Engn Claremont CA 91711 USA Univ Complutense Madrid Dept Comp Architecture & Automat Madrid Spain Imaginat Technol Ltd Kings Langley WD4 8LZ Herts England

In this study, the authors introduce MIPSfpga and its accompanying set of learning materials. MIPSfpga is a teaching infrastructure that offers access to the non-obfuscated Register-Transfer Level (RTL) source code of the MIPS microAptiv UP processor. The core is made available by Imagination Technologies for academic use and is targeted to a field-programmable gate array (FPGA), making it ideal for both the classroom and research. The supporting materials and labs focus on hands-on learning that emphasises computer architecture, system on chip (SoC) design and hardware-software codesign. Among other things, students learn to set up the MIPS soft-core processor on an FPGA, run and debug programs on the core in simulation and in hardware, add new peripherals to the system, understand the microarchitecture and extend it to support new features, experiment with different cache sizes and content management policies, add new instructions using the CorExtend interface available in MIPS processors, and understand SoCs in embedded systems and how they are designed and built up in layers to run complex software such as Linux.

关键词： field programmable gate arrays microprocessor chips computer science education computer architecture learning (artificial intelligence) source code (software) system-on-chip hardware-software codesign electronic engineering education MIPSfpga commercial MIPS soft-core processor computer architecture education learning materials teaching infrastructure nonobfuscated RTL source code MIPS microAptiv UP processor Imagination Technologies academic use field-programmable gate array hands-on learning system on chip SoC hardware-software codesign program debugging cache sizes content management policies CorExtend interface Linux

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High-performance implementation of in-network traffic pacing for small-buffer networks

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COMPUTER COMMUNICATIONS 2013年第13期36卷 1450-1459页

作者： Hanay, Y. Sinan Dwaraki, Abhishek Hu, Kekai Wolf, Tilman NICT Ctr Informat & Neural Networks Osaka Japan Osaka Univ Adv Network Architecture Res Lab Osaka Japan Univ Massachusetts Dept Elect & Comp Engn Amherst MA 01003 USA

Demands on data communication networks continue to drive the need for increasingly faster link speeds. Optical packet switching networks promise to provide data rates that are sufficiently high to satisfy the needs of the future Internet core network. However, a key technological problem with optical packet switching is the very small size of packet buffers that can be implemented in the optical domain. Existing protocols, for example the widely used Transmission Control Protocol (TCP), do not perform well in such small-buffer networks. To address this problem, we have proposed techniques for actively pacing traffic at edge networks to ensure that traffic bursts are reduced or eliminated and thus do not cause packet losses in routers with small buffers. We have also shown that this traffic pacing can improve the performance of conventional networks that use small buffers (e.g., to reduce the cost of buffer memory on routers). A key challenge in this context is to develop systems that can perform such packet pacing efficiently and at high data rates. In this paper, we present the design and prototype of a hardware implementation of our packet pacing technique. We discuss and evaluate design trade-offs and present performance results from an prototype implementation based on a NetFPGA fieldprogrammable gate array system. Our results show that traffic pacing can be implemented with few hardware resources and without reducing system throughput. Therefore, we believe that traffic pacing can be deployed widely to improve the operation of current and future networks. (c) 2013 Elsevier B.V. All rights reserved.

关键词： Small-buffer network Traffic pacing Traffic burstiness field-programmable gate array Prototype

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Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing

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PROCEEDINGS OF THE IEEE 2016年第10期104卷 1844-1863页

作者： Hanyu, Takahiro Endoh, Tetsuo Suzuki, Daisuke Koike, Hiroki Ma, Yitao Onizawa, Naoya Natsui, Masanori Ikeda, Shoji Ohno, Hideo Tohoku Univ Elect Commun Res Inst Sendai Miyagi 9807577 Japan Tohoku Univ Ctr Spintron Integrated Syst Sendai Miyagi 9808577 Japan Tohoku Univ Ctr Innovat Integrated Elect Syst Sendai Miyagi 9800845 Japan Tohoku Univ Grad Sch Engn Sendai Miyagi 9808579 Japan Tohoku Univ Frontier Res Inst Interdisciplinary Sci Sendai Miyagi 9808578 Japan

Nonvolatile spintronic devices have potential advantages, such as fast read/write and high endurance together with back-end-of-the-line compatibility, which offers the possibility of constructing not only stand-alone RAMs and embedded RAMs that can be used in conventional VLSI circuits and systems but also standby-power-free high-performance nonvolatile CMOS logic employing logic-in-memory architecture. The advantages of employing spintronic devices, especially magnetic tunnel junction (MTJ) devices with CMOS circuits, are discussed, and the current status of the MTJ-based VLSI computing paradigm is presented along with its prospects and remaining challenges.

关键词： field-programmable gate array image recognition logic-in-memory architecture magneto-resistive RAM microcontroller unit (MCU) MTJ device MTJ/MOS-hybrid circuit nonvolatile LSI power gating standby power ternary content-addressable memory

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SIKE'd Up: Fast Hardware Architectures for Supersingular Isogeny Key Encapsulation

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2020年第12期67卷 4842-4854页

作者： Koziel, Brian Ackie, A-Bon Khatib, Rami El Azarderakhsh, Reza Kermani, Mehran Mozaffari Florida Atlantic Univ CEECS Dept Boca Raton FL 33431 USA Univ S Florida CSE Dept Tampa FL 33620 USA

In this work, we present a fast parallel architecture to perform supersingular isogeny key encapsulation (SIKE). We propose and implement a fast isogeny accelerator architecture that uses fast and parallelized isogeny formulas. On top of our isogeny accelerator, we build a novel architecture for the SIKE primitive, which provides both quantum and IND-CCA security. We synthesized this architecture on the Xilinx Artix-7, Virtex-7, and Kintex UltraScale+ FPGA families. Over Virtex-7 FPGA's, our constant-time implementations are roughly 14% faster than the state-of-the-art with a better area-time product. At the NIST security level 5 on a Kintex UltraScale+ FPGA, we can execute the entire SIKE protocol in 15.3 ms. This work continues to improve the speed of isogeny-based computations and also features all parameter sets of the SIKE round 2 specification, with results applicable to NIST's post-quantum standardization process.

关键词： Elliptic curves NIST field programmable gate arrays Public key Computer architecture field-programmable gate array isogeny-based cryptography post-quantum cryptography SIKE

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Algorithm for realisation, parameter analysis, and measurement of pipelined separable 3D finite impulse response filters composed of Givens rotation structures

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IET SIGNAL PROCESSING 2018年第7期12卷 857-867页

作者： Poczekajlo, Pawel Wawryn, Krzysztof Koszalin Univ Technol Fac Elect & Comp Sci PL-75453 Koszalin Poland

A novel algorithm for the realisation of an orthogonal digital system performing three-dimensional filtering for a separable transfer function is presented in this study. The algorithm is based on a state-space approach and consists of synthesis and implementation algorithms. A structure composed of Givens rotators and delay elements is obtained. A coordinate rotation digital computer algorithm has been used to implement Givens rotators in a pipelined structure. The obtained structure has been realised on a field-programmable gate array (FPGA) chip and its performance has been evaluated. It achieved good finite precision, good sensitivity of filter amplitude to filter coefficients, less noise, better impulse response, and less FPGA chip occupation. To verify the obtained results, they have been compared to the results obtained using a direct-form structure consisting of adders, multipliers, and delay elements.

关键词： FIR filters transfer functions field programmable gate arrays pipeline processing parameter analysis pipelined separable 3D finite impulse response filter Givens rotation structure orthogonal digital system three-dimensional filtering separable transfer function state-space approach coordinate rotation digital computer algorithm field-programmable gate array FPGA chip occupation

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Evolutionary design of hash function pairs for network filters

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APPLIED SOFT COMPUTING 2017年 56卷 173-181页

作者： Dobai, Roland Korenek, Jan Sekanina, Lukas Brno Univ Technol Fac Informat Technol Ctr Excellence IT4Innovat Brno Czech Republic

Network filtering is a challenging area in high-speed computer networks, mostly because lots of filtering rules are required and there is only a limited time available for matching these rules. Therefore, network filters accelerated by field-programmable gate arrays (FPGAs) are becoming common where the fast lookup of filtering rules is achieved by the use of hash tables. It is desirable to be able to fill-up these tables efficiently, i.e. to achieve a high table-load factor in order to reduce the offline time of the network filter due to rehashing and/or table replacement. A parallel reconfigurable hash function tuned by an evolutionary algorithm (EA) is proposed in this paper for Internet Protocol (IP) address filtering in FPGAs. The EA fine-tunes the reconfigurable hash function for a given set of IP addresses. The experiments demonstrate that the proposed hash function provides high-speed lookup and achieves a higher table-load factor in comparison with conventional solutions. (C) 2017 Elsevier B.V. All rights reserved.

关键词： Evolutionary algorithm Hash function Network filter field-programmable gate array Cuckoo

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Multilevel NoSQL Cache Combining In-NIC and In-Kernel Approaches

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IEEE MICRO 2017年第5期37卷 44-51页

作者： Tokusashi, Yuta Matsutani, Hiroki Keio Univ Tokyo Japan Keio Univ Dept Informat & Comp Sci Tokyo Japan

Key-value store accelerators based on field-programmable gate arrays (FPGAs) have been proposed to achieve higher performance per watt than software-based processing. However, both their cache capacity and application domains are limited. The authors' proposed multilevel NoSQL cache architecture utilizes both an FPGA-based hardware cache and a complementary in-kernel software cache. Their design reduces the cache miss ratio and improves throughput compared to the nonhierarchical design.

关键词： Accelerators field programmable gate arrays field-programmable gate array FPGA key-value store NoSQL Random access memory

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Asynchronous control and driver for high-speed LED display with local scanning approach

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IET CIRCUITS DEVICES & SYSTEMS 2020年第1期14卷 1-6页

作者： Hsia, Shih-Chang Lin, Yu-Cheng Wong, Wing-Kwong Hsu, Ren-Chien Natl Yunlin Univ Sci & Technol Dept Elect 123 Univ RdSect 3 Touliu Taiwan

This study presents an extendable full-colour light emitting diode (LED) display based on field-programmable gate array implementation. The LED display panel system includes memory management, image format conversion, serial parallel interface (SPI) interface, local scan techniques, LED driver and pulse width modulation (PWM) data control. To reduce I/O ports, data transmission system uses SPI interface to send the PWM data to the LED panels. A novel local scan technique, which could use a lower frequency for data transmission and achieve higher frame rate for LED display, is proposed. Each display module contains local memories for data self-scanning to LED. The display continues even if there is no new data input. The advantages are that the display rate does not care about the speed of data transmission. Only motion area, rather than complete frame, required sending data to display, which can greatly improve data bandwidth. This is very useful for high-resolution display system since even low data rate can achieve the fast display refresh. This approach is a module-based design, which can easily be extended to any size with auto re-configuration without using embedded processor.

关键词： field programmable gate arrays LED displays driver circuits asynchronous circuits data transmission system SPI interface local scan technique display module high-resolution display system high-speed LED display local scanning approach extendable full-colour light LED display panel system memory management pulse width modulation field-programmable gate array asynchronous control asynchronous driver light emitting diode image format conversion LED driver PWM data control I O ports embedded processor

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