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field-programmable gate array-based intelligent dynamic sliding-mode control using recurrent wavelet neural network for linear ultrasonic motor

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IET CONTROL THEORY AND APPLICATIONS 2010年第9期4卷 1511-1532页

作者： Lin, F. -J. Hung, Y. -C. Chen, S. -Y. Natl Cent Univ Dept Elect Engn Chungli 320 Taiwan

A field-programmable gate array (FPGA)-based intelligent dynamic sliding-mode control (IDSMC) using recurrent wavelet neural network (RWNN) estimator is proposed to control the mover position of a linear ultrasonic motor (LUSM) in this study. First, the structure and operating principles of the LUSM are introduced briefly. Then, the dynamics of LUSM mechanism with the introduction of a lumped uncertainty, which include the friction force, is derived. Since the dynamic characteristics and motor parameters of the LUSM are non-linear and time-varying, an IDSMC using RWNN estimator is designed to achieve robust control performance of the LUSM drive system. The RWNN estimator is employed to estimate the non-linear functions including the system parameters and external disturbance. Moreover, the adaptive learning algorithm trained the parameters of the RWNN online is derived using the Lyapunov stability theorem. Furthermore, an FPGA chip is adopted to implement the developed control and on-line learning algorithms for possible low-cost and high-performance industrial applications. The experimental results show that excellent positioning and tracking performance are achieved. In addition, the robustness to parameter variations and friction force can be obtained as well using the proposed control system.

关键词： linear motors friction force adaptive control Control of electric power systems intelligent dynamic sliding-mode control lumped uncertainty recurrent neural nets Multivariable control systems ultrasonic motors neurocontrollers Logic and switching circuits variable structure systems Stability in control theory control system synthesis Linear machines Control system analysis and synthesis methods control engineering electric machine analysis computing Logic circuits recurrent wavelet neural network robust control field programmable gate arrays Self-adjusting control systems Lyapunov methods Control engineering computing machine control Neurocontrol uncertain systems Piezoelectric motors field-programmable gate array adaptive learning algorithm Power engineering computing linear ultrasonic motor Lyapunov stability theorem

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field-programmable gate array-based functional link radial basis function network control for permanent magnet linear synchronous motor servo drive system

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IET ELECTRIC POWER APPLICATIONS 2010年第5期4卷 357-372页

作者： Lin, F. -J. Chou, P. -H. Hung, Y. -C. Wang, W. -M. Natl Cent Univ Dept Elect Engn Chungli 320 Taiwan Natl Dong Hwa Univ Dept Elect Engn Hualien 974 Taiwan

A field-programmable gate array (FPGA)-based functional link radial basis function network (FLRBFN) control is proposed in this study to control the mover of a permanent magnet linear synchronous motor (PMLSM) servo drive system to track periodic reference trajectories. First, the dynamics of the field-oriented control PMLSM servo drive with a lumped uncertainty, which contains parameter variations, external disturbances and non-linear friction force, is derived. Then, to achieve accurate trajectory tracking performance with robustness, an intelligent control approach using FLRBFN is proposed for the field-oriented control PMLSM servo drive system. The proposed FLRBFN is a radial basis function network (RBFN) embedded with a functional link neural network (FLNN). Moreover, the on-line learning algorithm of the FLRBFN, including the connective weights, the centres and the centres' width of the receptive field functions, are derived using back-propagation (BP) method. Furthermore, an FPGA chip is adopted to implement the developed control and on-line learning algorithms for possible low-cost and high-performance industrial applications using PMLSM. Finally, the effectiveness of the proposed control scheme and the robustness to parameter variations, external disturbances and friction force of the PMLSM servo drive system are verified by some experimental results.

关键词： field-oriented control linear motors machine vector control Control of electric power systems backpropagation method lumped uncertainty FPGA neurocontrollers permanent magnet linear synchronous motor servo drive system synchronous motor drives Linear machines Actuating and final control devices trajectory tracking performance RBFN functional link radial basis function network control field programmable gate arrays servomechanisms permanent magnet motors Synchronous machines Neurocontrol field-programmable gate array backpropagation radial basis function networks nonlinear friction force intelligent control approach Drives

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A Flexible FPGA-Based Quasi-Cyclic LDPC Decoder

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IEEE ACCESS 2017年 5卷 20965-20984页

作者： Hailes, Peter Xu, Lei Maunder, Robert G. Al-Hashimi, Bashir M. Hanzo, Lajos Univ Southampton Sch Elect & Comp Sci Southampton SO17 1BJ Hants England Intel Corp Programmable Solut Grp San Jose CA 95134 USA

Low-density parity check (LDPC) error correction decoders have become popular in diverse communications systems, owing to their strong error correction performance and their suitability to parallel hardware implementation. A great deal of research effort has been invested into the implementation of LDPC decoder designs on field-programmable gate array (FPGA) devices, in order to exploit their high processing speed, parallelism, and re-programmability. Meanwhile, a variety of application-specific integrated circuit implementations of multi-mode LDPC decoders exhibiting both inter-standard and intra-standard reconfiguration flexibility are available in the open literature. However, the high complexity of the adaptable routing and processing elements that are required by a flexible LDPC decoder has resulted in a lack of viable FPGA-based implementations. Hence in this paper, we propose a parameterisable FPGA-based LDPC decoder architecture, which supports run-time flexibility over any set of one or more quasi-cyclic LDPC codes. Additionally, we propose an off-line design flow, which may be used to automatically generate an optimized HDL description of our decoder, having support for a chosen selection of codes. Our implementation results show that the proposed architecture achieves a high level of design-time and run-time flexibility, whilst maintaining a reasonable processing throughput, hardware resource requirement, and error correction performance.

关键词： Digital communication error correction codes low-density parity check (LDPC) codes field-programmable gate array iterative decoding

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Hardware implementation and comparison of displacement retrieval algorithms for a laser diode-based optical feedback interferometric sensor

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TURKISH JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES 2018年第4期26卷 1820-1832页

作者： Rehman, Ghazi Zabit, Usman Ullah, Muhammad Obaid Univ Engn & Technol Fac Elect & Elect Engn Dept Elect Engn Taxila Pakistan Natl Univ Sci & Technol Dept Elect Engn Islamabad Pakistan

Optical feedback interferometer (OFI) lasers, also called self-mixing (SM) lasers, have been widely explored over the last couple of decades due to their low cost, compactness, and self-aligned nature and they provide a very good solution for measurements of displacement, vibration, distance, velocity, etc. The SM effect takes place when a part of the laser beam is fed back to the active laser cavity after reflecting from the target. The reflected beam interferes with the emitted beam and hence the optical and spectral characteristics of the laser get changed. To retrieve the vibration or displacement signal of the target from the SM signal, different postprocessing algorithms have been proposed, such as the phase unwrapping method (PUM). The first step of the PUM leads to the coarse estimation of the laser phase and the final step is an iterative joint estimation of 2 parameters, namely laser coupling coefficient C and linewidth enhancement factor alpha. To make this algorithm applicable for real-time measurements, parallel joint estimation for a wide range of C and alpha values needs to be done. In this research, 3 algorithms, namely PUM, direct fringe unwrapping (DFU), and improved DFU (IDFU) were tested for FPGA implementation by using Verilog HDL (hardware description language) so that more precise and real-time vibration and displacement signals of targets could be extracted from the SM sensor in an embedded systems environment. These algorithms were developed using Verilog HDL for implementation on the Xilinx Spartan-3 Xcs400-FG320 development board. Our designed IDFU algorithm performed 0:492 times better than the parallel PUM algorithm in maximum clock frequency and 1:53 and 1:21 times better than the PUM in slice registers and LUT utilization of hardware resources, respectively. The designed DFU algorithm can operate 1:355 times better than IDFU in maximum clock frequency and 25:34 and 14:25 times better than IDFU in slice registers and LUT utilization of

关键词： Self-mixing laser sensors real time phase unwrapping method direct fringe unwrapping improved direct fringe unwrapping field-programmable gate array

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FPGA-Based Controller for a Permanent-Magnet Synchronous Motor Drive Based on a Four-Level Active-Clamped DC-AC Converter

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ENERGIES 2018年第10期11卷

作者： Nicolas-Apruzzese, Joan Lupon, Emili Busquets-Monge, Sergio Conesa, Alfonso Bordonau, Josep Garcia-Rojas, Gabriel Univ Politecn Cataluna Elect Engn Dept E-08028 Barcelona Spain

This paper proposes a closed-loop control implementation fully-embedded into an FPGA for a permanent-magnet synchronous motor (PMSM) drive based on a four-level active-clamped converter. The proposed FPGA controller comprises a field-oriented control to drive the PMSM, a DC-link voltage balancing closed-loop control (VBC), and a virtual-vector-based modulator for a four-level active-clamped converter. The VBC and the modulator operate in consonance to preserve the DC-link capacitor voltages balanced. The FPGA design methodology is carefully described and the main aspects to achieve an optimal FPGA implementation using low resources are discussed. Experimental results under different operating conditions are presented to demonstrate the good performance and the feasibility of the proposed controller for motor-drive applications.

关键词： DC-link voltage balancing field-oriented control field-programmable gate array multilevel active-clamped converter motor drive

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A TIME-DOMAIN PULSE AMPLITUDE AND WIDTH DISCRIMINATION METHOD FOR PHOTON COUNTING

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METROLOGY AND MEASUREMENT SYSTEMS 2018年第2期25卷 269-282页

作者： del Mar Correa, Maryam Perez, Freddy R. Univ Pondficia Bolivariana Ctr Ciencia Basica Grp Opt & Espect Circular 1 70-01 Medellin Colombia

This work shows a time-domain method for the discrimination and digitization of parameters of voltage pulses coming from optical detectors, taking into account the presence of electronic noise and afterpulsing. Our scheme is based on an FPGA-based time-to-digital converter as well as an adjustable-threshold comparator complemented with commercial elements. Here, the design, implementation and optimization of a multiphase TDC using delay lines shorter than a single clock period is also described. The performance of this signal processing system is discussed through the results from the statistical code density test, statistical distributions of measurements and information gathered from an optical detector. Unlike dual voltage threshold discriminators or constant-fraction discriminators, the proposed method uses amplitude and time information to define an adjustable discrimination window that enables the acquisition of spectra.

关键词： field-programmable gate array time-to-digital converter spectroscopy photomultiplier photon counting discriminator after-pulsing low-voltage differential signalling

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FPGA-Based Implementation of MMC Control Based on Sorting Networks

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ENERGIES 2018年第9期11卷

作者： Ricco, Mattia Mathe, Laszlo Monmasson, Eric Teodorescu, Remus Aalborg Univ Dept Energy Technol DK-9100 Aalborg Denmark Cergy Pontoise Univ SATIE Lab F-95031 Cergy Pontoise France

In Modular Multilevel Converter (MMC) applications, the balancing of the capacitor voltages is one of the most important issues for achieving the proper behavior of the MMC. The Capacitor Voltage Balancing (CVB) control is usually based on classical sorting algorithms which consist of repetitive/recursive loops. This leads to an increase of the execution time when many Sub-Modules (SMs) are employed. When the execution time of the balancing is longer than the sampling period, the proper operation of the MMC cannot be ensured. Moreover, due to their inherent sequential operation, sorting algorithms are suitable for software implementation (microcontrollers or DSPs), but they are not appropriate for a hardware implementation. Instead, in this paper, Sorting Networks (SNs) are proposed due to their convenience for implementation in FPGA devices. The advantages and the main challenges of the Bitonic SN in MMC applications are discussed and different FPGA implementations are presented. Simulation results are provided in normal and faulty conditions. Moreover, a comparison with the widely used bubble sorting algorithm and max/min approach is made in terms of execution time and performance. Finally, hardware-in-the-loop results are shown to prove the effectiveness of the implemented SN.

关键词： modular multilevel converters capacitor voltage balancing sorting networks field-programmable gate array

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High-performance and high-speed implementation of polynomial basis Itoh-Tsujii inversion algorithm over GF(2^m)

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IET INFORMATION SECURITY 2017年第2期11卷 66-77页

作者： Rashidi, Bahram Farashahi, Reza Rezaeian Sayedi, Sayed Masoud Isfahan Univ Technol Dept Elect & Comp Engn Esfahan *** Iran Isfahan Univ Technol Dept Math Sci Esfahan *** Iran Inst Res Fundamental Sci IPM Sch Math POB 19395-5746 Tehran Iran

In this study high-performance and high-speed field-programmable gate array (FPGA) implementations of polynomial basis Itoh-Tsujii inversion algorithm (ITA) over GF(2(m)) constructed by irreducible trinomials and pentanomials are presented. The proposed structures are designed by one field multiplier and k-times squarer blocks or exponentiation by 2(k), where k is a small positive integer. The k-times squarer blocks have an efficient tree structure with low critical path delay, and the multiplier is based on a proposed high-speed digit-serial architecture with minimum hardware resources. Furthermore, to reduce the computation time of ITA, the critical path of the circuit is broken to finer path using several registers. The computation times of the structure on Virtex-4 FPGA family are 0.262, 0.192 and 0.271 mu s for GF(2(163)), GF(2(193)) and GF(2(233)), respectively. The comparison results with other implementations of the polynomial basis Itoh-Tsujii inversion algorithm verify the improvement in the proposed architecture in terms of speed and performance.

关键词： field programmable gate arrays polynomials multiplying circuits flip-flops trees (mathematics) logic design Virtex-4 FPGA family registers hardware resources digit-serial architecture path delay tree structure k-times squarer blocks field multiplier pentanomials irreducible trinomials field-programmable gate array ITA polynomial basis Itoh-Tsujii inversion algorithm

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FPGA implementation of hardware efficient adaptive filter robust to impulsive noise

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IET COMPUTERS AND DIGITAL TECHNIQUES 2017年第3期11卷 107-116页

作者： Parmar, Chintan A. Ramanadham, Bhaskar Darji, Anand D. SVNIT Elect Dept Surat India

Adaptive filters are prevalent in many real-time signal processing applications. Many adaptive algorithms already exist, but most of them assume white Gaussian noise as disturbance. However, for many applications such as electrocardiogram, foetus heart rate measurement, low frequency atmospheric noise, underwater acoustic noise and signal measurement in instrumentation, the impulsive noise is more common. This study presents a modified robust mixed norm (MRMN) adaptive filter algorithm robust to impulsive noise with higher convergence rate and lower steady state error (SSE). MRMN adaptive filter algorithm has been simulated using Matlab and Xilinx system generator high level synthesis tool and a significant improvement in SSE and convergence speed is obtained compared with the existing adaptive filter algorithms for similar specifications. The proposed algorithm is also described using VHDL and synthesised using Xilinx synthesiser tool in order to implement on field-programmable gate array (FPGA). The FPGA post route and place implementation results show nearly 90% reduction in resource utilisation and nearly 2.6 times improvement in clock frequency as compared with the existing FPGA based implementation for similar specifications.

关键词： convergence rate Xilinx system generator high level synthesis tool modified robust mixed norm filter FPGA steady state error Logic and switching circuits Digital signal processing impulsive noise VHDL hardware description languages Logic circuits field programmable gate arrays impulse noise convergence MRMN adaptive filter algorithm Filtering methods in signal processing field-programmable gate array SSE adaptive filters Matlab hardware efficient adaptive filter

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Optimizing FPGA-based CNN accelerator for energy efficiency with an extended Roofline model

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TURKISH JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES 2018年第2期26卷 919-935页

作者： Ayat, Sayed Omid Khalil-Hani, Mohamed Ab Rahman, Ab Al-Hadi Univ Teknol Malaysia Fac Elect Engn VeCAD Res Lab Skudai Johor Malaysia

In recent years, the convolutional neural network (CNN) has found wide acceptance in solving practical computer vision and image recognition problems. Also recently, due to its flexibility, faster development time, and energy efficiency, the field-programmable gate array (FPGA) has become an attractive solution to exploit the inherent parallelism in the feedforward process of the CNN. However, to meet the demands for high accuracy of today's practical recognition applications that typically have massive datasets, the sizes of CNNs have to be larger and deeper. Enlargement of the CNN aggravates the problem of off-chip memory bottleneck in the FPGA platform since there is not enough space to save large datasets on-chip. In this work, we propose a memory system architecture that best matches the off-chip memory traffic with the optimum throughput of the computation engine, while it operates at the maximum allowable frequency. With the help of an extended version of the Roofline model proposed in this work, we can estimate memory bandwidth utilization of the system at different operating frequencies since the proposed model considers operating frequency in addition to bandwidth utilization and throughput. In order to find the optimal solution that has the best energy efficiency, we make a trade-off between energy efficiency and computational throughput. This solution saves 18% of energy utilization with the trade-off having less than 2% reduction in throughput performance. We also propose to use a race-to-halt strategy to further improve the energy efficiency of the designed CNN accelerator. Experimental results show that our CNN accelerator can achieve a peak performance of 52.11 GFLOPS and energy efficiency of 10.02 GFLOPS/W on a ZYNQ ZC706 FPGA board running at 250 MHz, which outperforms most previous approaches.

关键词： Convolutional neural network field-programmable gate array energy efficiency Roofline model race-to-halt strategy

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