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JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 2017年第7期26卷 1750125-1750125页

作者： Kolopienczyk, Malgorzata Titarenko, Larysa Barkalov, Alexander Univ Zielona Gora Inst Control & Computat Engn Licealna 9 PL-65417 Zielona Gora Poland Univ Zielona Gora Inst Metrol Elect & Comp Sci Licealna 9 PL-65417 Zielona Gora Poland

The complexity of algorithms implemented in digital systems grows. Methods are developed for most effective use of both hardware resources and energy. For engineers the problem of hardware resources optimization in design of control units is still an important issue. The standard way of implementing the control unit as a finite-state machine (FSM) is not satisfactory as it consumes considerable amounts of field-programmable gate arrays (FPGA) resources. This paper is devoted to the design of a Moore FSM in FPGA structure using look-up tables and embedded memory blocks (EMB) elements. The problem background is discussed. The method of the design of Moore FSM logic circuits with EMB based on splitting the set of logical conditions and the encoding of logical conditions is presented. Examples of design and research results are given.

关键词： Finite-state machine field-programmable gate array design logic circuit

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Synthesizable Standard Cell FPGA Fabrics Targetable by the Verilog-to-Routing CAD Flow

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ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS 2017年第2期10卷 11-11页

作者： Kim, Jin Hee Anderson, Jason H. Univ Toronto Dept Elect & Comp Engn 10 Kings Coll Rd Toronto ON M5S 3G4 Canada

In this article, we consider implementing field-programmable gate arrays (FPGAs) using a standard cell design methodology and present a framework for the automated generation of synthesizable FPGA fabrics. The open-source Verilog-to-Routing (VTR) FPGA architecture evaluation framework [Rose et al. 2012] is extended to generate synthesizable Verilog for its in-memory FPGA architectural device model. The Verilog can subsequently be synthesized into standard cells, placed and routed using an ASIC design flow. A second extension to VTR generates a configuration bitstream for the FPGA, where the bitstream configures the FPGA to realize a user-provided placed and routed design. The proposed framework and methodology makes possible the silicon implementation of a wide range of VTR-modeled FPGA fabrics. In an experimental study, area and timing-optimized FPGA implementations in 65nm TSMC standard cells are compared to a 65nm Altera commercial FPGA. In addition, we consider augmenting the generic standard-cell library from TSMC with a manually designed and laid-out FPGA-specific cell. We demonstrate the utility of the custom cell in reducing the area of the synthesized FPGA fabric.

关键词： field-programmable gate array

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An experimental study of coarse-grained reconfigurable system-on-chip-based software-defined radio

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TURKISH JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES 2016年第3期24卷 1176-1193页

作者： Nithiyanantham, Janakiraman Palanisamy, Nirmal Kumar Anna Univ Dept Elect & Commun Engn Fac Informat & Commun Engn Madras 600025 Tamil Nadu India

Software-defined radio (SDR) research deals with a mixture of hardware and software technologies, where RF operating parameters and components are to be set or altered by modifiable software or firmware. This paper describes the coarse-grained reconfigurable array (CGRA) implementations of SDR architecture. This architecture is an extension of traditional SDR in complex adaptation strategies, such as highly reliable communications and efficient utilization of the resources and spectrum upgrade, through its internal states (performance) and hardware architecture. The proposed CGRA-based SDR implementation is based on dynamic partial reconfiguration methodology, which has the capability of reusing the same hardware module to handle different algorithms. This CGRA-based SDR provides greater flexibility and adds new abilities without additional cost. Initially, the SDR system was simulated in the Agilent SystemVue environment to analyze the error boundaries of the proposed SDR architecture. Then the SDR system was coded in the Verilog hardware description language and implemented on top of CGRAs such as the MOLEN, MORPHOSYS, and ADRES reconfigurable system-on-chip (SoC) architectures. These SoC architectures were installed within the Xilinx Virtex 5 field-programmable gate array to analyze the performance of SDR architectures in terms of area utilization, operational speed, power optimization, reconfiguration time, coprocessor execution time, preemption support, and relocation support of the system. The performance analysis indicates that the ADRES SoC architecture is suitable for dynamic partial reconfiguration and the MOLEN SoC architecture is more suitable for power, area, and speed requirements and low circuit complexity compared to other architectures.

关键词： Software-defined radio reconfigurable architecture field-programmable gate array system-on-chip MOLEN MORPHOSYS ADRES

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Fast and accurate FPGA-based framework for processor architecture vulnerability analysis

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INTEGRATION-THE VLSI JOURNAL 2016年第Mar.期53卷 14-26页

作者： Mahdiani, Hoda Safari, Saeed Salehi, Mostafa E. Univ Tehran Sch Elect & Comp Engn Tehran 14395515 Iran

This paper presents a fast, accurate, and flexible FPGA-based fault emulation platform, namely FARAVAM that can be exploited for AVF analysis in modern microprocessors. The proposed approach provides fault injection capabilities supporting automatic modification of post-synthesis net-lists and introduces a highly controllable and observable transient fault analysis environment. The presented vulnerability analysis platform using both exhaustive and random fault emulation approaches, provides useful information for identifying areas threatening reliability to make processors more fault tolerant. We applied our platform for extracting the best trade-offs between precision and speed up in vulnerability analysis of MIPS processor. The experimental results indicate that in addition to having high precision we obtain about seven orders of magnitude speed up in comparison with simulation based vulnerability analysis techniques. (C) 2015 Elsevier B.V. All rights reserved.

关键词： Architecture Vulnerability analysis Soft error Embedded processors Fault modeling and emulation field-programmable gate array

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Frequency domain near-infrared multiwavelength imager design using high-speed, direct analog-to-digital conversion

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JOURNAL OF BIOMEDICAL OPTICS 2016年第1期21卷 1-8页

作者： Zimmermann, Bernhard B. Fang, Qianqian Boas, David A. Carp, Stefan A. Harvard Med Sch Massachusetts Gen Hosp Athinoula A Martinos Ctr Biomed Imaging Bldg 14913th St Charlestown MA 02129 USA MIT Dept Elect Engn & Comp Sci 77 Massachusetts Ave Cambridge MA 02139 USA Northeastern Univ Dept Bioengn 360 Huntington Ave Boston MA 02115 USA

Frequency domain near-infrared spectroscopy (FD-NIRS) has proven to be a reliable method for quantification of tissue absolute optical properties. We present a full-sampling direct analog-to-digital conversion FD-NIR imager. While we developed this instrument with a focus on high-speed optical breast tomographic imaging, the proposed design is suitable for a wide-range of biophotonic applications where fast, accurate quantification of absolute optical properties is needed. Simultaneous dual wavelength operation at 685 and 830 nm is achieved by concurrent 67.5 and 75 MHz frequency modulation of each laser source, respectively, followed by digitization using a high-speed (180 MS/s) 16-bit A/D converter and hybrid FPGA-assisted demodulation. The instrument supports 25 source locations and features 20 concurrently operating detectors. The noise floor of the instrument was measured at <1.4 pW/root Hz, and a dynamic range of 115+ dB, corresponding to nearly six orders of magnitude, has been demonstrated. Titration experiments consisting of 200 different absorption and scattering values were conducted to demonstrate accurate optical property quantification over the entire range of physiologically expected values. (C) 2016 Society of Photo-Optical Instrumentation Engineers (SPIE)

关键词： radio frequency diffuse near-infrared light full sampling field-programmable gate array absolute optical property breast cancer

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Highly Sensitive FPW-Based Microsystem for Rapid Detection of Tetrahydrocannabinol in Human Urine

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SENSORS 2017年第12期17卷 2760-2760页

作者： Lan, Je-Wei Hsieh, Chia-Hsu Huang, I-Yu Lin, Yu-Cheng Tsai, Tsung-Yi Wang, Chua-Chin Natl Sun Yat Sen Univ Dept Elect Engn Kaohsiung 80424 Taiwan Natl Cheng Kung Univ Dept Engn Sci Tainan 70101 Taiwan

This paper presents a highly sensitive flexural plate-wave (FPW)-based microsystem for rapid detection of tetrahydrocannabinol (THC) in human urine. First, a circular-type interdigital transducer (IDT) was integrated with a circular-type silicon-grooved reflective grating structure (RGS) to reduce insertion loss. Then, with lower insertion loss (-38.758 dB), the FPW device was used to develop a novel THC biosensor, and the results reveal that this FPW-THC biosensor has low detection limit (1.5625 ng/mL) and high mass-sensitivity (126.67 cm(2)/g). Finally, this biosensor was integrated with field-programmable gate array (FPGA) board and discrete components for prototyping a FPW readout system, whose maximum error was 12.378 kHz to ensure that the linearity of detection up to R-square is equal to 0.9992.

关键词： flexural plate-wave tetrahydrocannabinol circular-type interdigital transducer reflective grating structure low insertion loss field-programmable gate array readout system

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Design and Implementation of an FPGA-based Real-time Simulator for a Dual Three-Phase Induction Motor Drive

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JOURNAL OF POWER ELECTRONICS 2016年第2期16卷 553-563页

作者： Gregor, Raul Valenzano, Guido Rodas, Jorge Rodriguez-Pineiro, Jose Gregor, Derlis Univ Nacl Asuncion Fac Ingn Lab Power & Control Syst Asuncion Paraguay Univ A Coruna Dept Elect & Syst Coruna Spain Univ Nacl Asuncion Fac Ingn Lab Distributed Syst Asuncion Paraguay

This paper presents a digital hardware implementation of a real-time simulator for a multiphase drive using a field-programmable gate array (FPGA) device. The simulator was developed with a modular and hierarchical design using very high-speed integrated circuit hardware description language (VHDL). Hence, this simulator is flexible and portable. A state-space representation model suitable for FPGA implementations was proposed for a dual three-phase induction machine (DTPIM). The simulator also models a two-level 12-pulse insulated-gate bipolar transistor (IGBT)-based voltage-source converter (VSC), a pulse-width modulation scheme, and a measurement system. Real-time simulation outputs (stator currents and rotor speed) were validated under steady-state and transient conditions using as reference an experimental test bench based on a DTPIM with 15 kW-rated power. The accuracy of the proposed digital hardware implementation was evaluated according to the simulation and experimental results. Finally, statistical performance parameters were provided to analyze the efficiency of the proposed DTPIM hardware implementation method.

关键词： Device simulation field-programmable gate array Multiphase drive Real-time simulation

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ACHIEVING ONE BILLION KEY-VALUE REQUESTS PER SECOND ON A SINGLE SERVER

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IEEE MICRO 2016年第3期36卷 94-104页

作者： Li, Sheng Lim, Hyeontaek Lee, Victor W. Ahn, Jung Ho Kalia, Anuj Kaminsky, Michael Andersen, David G. Seongil, O. Lee, Sukhan Dubey, Pradeep Intel Labs Santa Clara CA 95054 USA Carnegie Mellon Univ Dept Comp Sci Pittsburgh PA 15213 USA Seoul Natl Univ Grad Sch Convergence Sci & Technol Seoul 151 South Korea Carnegie Mellon Univ Comp Sci Pittsburgh PA 15213 USA Seoul Natl Univ Seoul 151 South Korea Seoul Natl Univ Dept Transdisciplinary Studies Seoul 151 South Korea

To architect high-performance and efficient key-value store (KVS) platforms, the authors identify the critical hardware/software ingredients for high-performance KVS systems through rigorous full-stack (software through hardware) analysis, and suggest new optimizations to achieve record-setting throughput. Finally, they propose a future general-purpose many-core platform and demonstrate the capability of achieving a billion requests per second with a single server platform constructed following their principles.

关键词： Concurrency control field programmable analog arrays field-programmable gate array Key value systems key-value performance key-value store Memory management million requests per second Performance evaluation Program processors Servers

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Simple and robust self-healing technique for millimetre-wave amplifiers

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IET CIRCUITS DEVICES & SYSTEMS 2016年第1期10卷 37-43页

作者： Jia, Haikun Chi, Baoyong Kuang, Lixue Wang, Zhihua Tsinghua Univ Inst Microelect Beijing 100084 Peoples R China

A simple and robust self-healing technique for millimetre-wave (mm-wave) amplifiers is proposed. The self-healing technique can correct the operation frequency shifting of the amplifier (including its input and output impedance matching shifting) due to process, voltage, and temperature variations and modelling inaccuracy. A mm-wave amplifier with digitally controlled artificial dielectric transmission lines as fine frequency tuning components and an on-chip power detector as the frequency shifting detector has been implemented in 65 nm complementary metal-oxide-semiconductor to verify the effectiveness of the technique. The operating frequency of five amplifier chips is calibrated by running the self-healing algorithm on a field-programmable gate array development board. On average, the gain of the amplifier is improved by 2.60 dB from 13.66 to 16.26 dB and the input matching is improved by 12.78 dB from -4.89 to -17.67 dB at 56 GHz after the proposed self-healing procedure.

关键词： digitally controlled artificial dielectric transmission line on-chip power detector dielectric materials self-healing technique operation frequency shifting complementary metal-oxide-semiconductor gain 13.66 dB to 16.26 dB mm-wave amplifier frequency tuning component millimetre-wave amplifier impedance matching field-programmable gate array circuit tuning transmission lines size 65 nm digital control impedance matching shifting temperature variation gain 2.6 dB CMOS integrated circuits field programmable gate arrays frequency shifting detector frequency 56 GHz amplifier chip millimetre wave amplifiers

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An Implementation of Multiple-Standard Video Decoder on a Mixed-Grained Reconfigurable Computing Platform

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IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS 2016年第5期E99D卷 1285-1295页

作者： Liu, Leibo Wang, Dong Chen, Yingjie Zhu, Min Yin, Shouyi Wei, Shaojun Tsinghua Univ Inst Microelect Beijing 100084 Peoples R China Beijing Jiaotong Univ Inst Informat Sci Beijing Peoples R China

This paper presents the design of a multiple-standard 1080 high definition (HD) video decoder on a mixed-grained reconfigurable computing platform integrating coarse-grained reconfigurable processing units (RPUs) and FPGAs. The proposed RPU, including 16 x 16 multi-functional processing elements (PEs), is used to accelerate compute-intensive tasks in the video decoding. A soft-core-based microprocessor array is implemented on the FPGA and adopted to speed-up the dynamic reconfiguration of the RPU. Furthermore, a mail-box-based communication scheme is utilized to improve the communication efficiency between RPUs and FPGAs. By exploiting dynamic reconfiguration of the RPUs and static reconfiguration of the FPGAs, the proposed platform achieves scalable performances and cost trade-offs to support a variety of video coding standards, including MPEG-2, AVS, H.264, and HEVC. The measured results show that the proposed platform can support H.264 1080 HD video streams at up to 57 frames per second (fps) and HEVC 1080 HD video streams at up to 52fps under 250MHz, at the same time, it achieves a 3.6x performance gain over an industrial coarse-grained reconfigurable processor for H. 264 decoding, and a 6.43x performance boosts over a general purpose processor based implementation for HEVC decoding.

关键词： algorithm mapping coarse-grained reconfigurable array field-programmable gate array reconfigurable computing video decoding

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