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Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing

PROCEEDINGS OF THE IEEE 2016年第10期104卷 1844-1863页

作者： Hanyu, Takahiro Endoh, Tetsuo Suzuki, Daisuke Koike, Hiroki Ma, Yitao Onizawa, Naoya Natsui, Masanori Ikeda, Shoji Ohno, Hideo Tohoku Univ Elect Commun Res Inst Sendai Miyagi 9807577 Japan Tohoku Univ Ctr Spintron Integrated Syst Sendai Miyagi 9808577 Japan Tohoku Univ Ctr Innovat Integrated Elect Syst Sendai Miyagi 9800845 Japan Tohoku Univ Grad Sch Engn Sendai Miyagi 9808579 Japan Tohoku Univ Frontier Res Inst Interdisciplinary Sci Sendai Miyagi 9808578 Japan

Nonvolatile spintronic devices have potential advantages, such as fast read/write and high endurance together with back-end-of-the-line compatibility, which offers the possibility of constructing not only stand-alone RAMs and embedded RAMs that can be used in conventional VLSI circuits and systems but also standby-power-free high-performance nonvolatile CMOS logic employing logic-in-memory architecture. The advantages of employing spintronic devices, especially magnetic tunnel junction (MTJ) devices with CMOS circuits, are discussed, and the current status of the MTJ-based VLSI computing paradigm is presented along with its prospects and remaining challenges.

关键词： field-programmable gate array image recognition logic-in-memory architecture magneto-resistive RAM microcontroller unit (MCU) MTJ device MTJ/MOS-hybrid circuit nonvolatile LSI power gating standby power ternary content-addressable memory

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Hot Chips 27 Highlights

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IEEE MICRO 2016年第2期36卷 64-69页

作者： Amirtharajah, Rajeevan Robatmili, Behnam Univ Calif Davis Elect & Comp Engn Dept Davis CA 95616 USA

This column discusses some of the designs and presentations from the 2015 Hot Chips Symposium. [ABSTRACT FROM AUTHOR]

关键词： 5G cloud computing datacenter deep learning field-programmable gate array global cache coherency graphics high-performance computing Hot Chips Internet of Things Moore's law multimedia silicon SoC social media Sparc system on chip wireless

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Improved ring oscillator PUF on FPGA and its properties

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MICROPROCESSORS AND MICROSYSTEMS 2016年第PartA期47卷 55-63页

作者： Kodytek, Filip Lorencz, Robert Bucek, Jiri Czech Tech Univ Fac Informat Technol Thakurova 9 Prague Czech Republic

PUFs (Physical Unclonable Function) are increasingly used in proposals of security architectures for device identification and cryptographic key generation. Many PUF designs for FPGAs proposed up to this day are based on ring oscillators (RO). The classical approach is to compare frequencies of ROs and produce a single output bit from each pair of ROs based on the result of comparison of their frequencies. This ROPUF design requires all ROs to be mutually symmetric and also the number of pairs of ROs is limited in order to preserve the independence of bits in the PUF response. This led us to design a new ROPUF on FPGA which is capable of generating multiple output bits from each pair of ROs and is also allowing to create higher number of pairs of ROs, thereby making the use of ROs more efficient than the classical approach. Our PUF design is based on selecting a particular part of a counter value and using it for the PUF output. By applying Gray code on the counter values, we have considerably improved the PUF's statistical properties. In principle, this PUF design does not need the ROs to be mutually symmetric, however, it is shown that this ROPUF design has significantly better properties with varying supply voltage when symmetric ROs are used. All of the presented measurements were performed on Digilent Basys 2 FPGA Boards (Xilinx Spartan3E-100 CP132). In this work, we provide a more detailed description of the PUF design on FPGA and the behaviour of ROs with varying supply voltage. Our proposed PUF architecture offers more output bits with required statistical properties from each RO pair than the classical approach, where frequencies of ROs are compared. The presented improvements significantly reduce the dependence on fluctuation of supply voltage. (C) 2016 Elsevier B.V. All rights reserved.

关键词： Physical unclonable function field-programmable gate array Ring oscillator

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Vehicle localization systems: towards low-cost architectures

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TURKISH JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES 2016年第4期24卷 2010-2027页

作者： Sakhi, Samir Elouardi, Abdelhafid Bouaziz, Samir Belhocine, Mahmoud Mil Polytech Sch Digital Syst Lab Algiers Algeria Univ Paris 11 Orsay France Ctr Dev Adv Technol Algiers Algeria

INS-GPS integration is a fundamental task used to enhance the accuracy of an inertial navigation system alone. However, its implementation complexity has been a challenge to most embedded systems. This paper proposes a low-cost FPGA-based INS-GPS integration system, which consists of a Kalman filter and a soft processor. Moreover, we also evaluate the navigation algorithm on a low-cost ARM processor. Processing times and localization accuracy are compared in both cases for single and double precision floating-point format. Experimental results show the advantages of the FPGA-based approach over the ARM-based approach. The proposed architecture can operate at 100 Hz and demonstrates the advantage of using FPGAs to design low-cost INS-GPS localization systems.

关键词： INS-GPS sensors integration Kalman filter field-programmable gate array hardcore and softcore processor

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Electrical and optical clock and data recovery in optical access networks: a comparative study

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INTERNATIONAL JOURNAL OF COMMUNICATION SYSTEMS 2016年第17期29卷 2555-2564页

作者： Abd El-Khaleq, Esraa El-Sayed, Yasmine Ismail, Tawfik Mostafa, Hassan Cairo Univ Dept Elect & Commun Fac Engn Giza Egypt Cairo Univ Natl Inst Laser Enhanced Sci Dept Engn Applicat Laser Giza Egypt

Clock and data recovery (CDR) is an essential part in high-speed telecommunication systems. The CDR is used to extract the clock and re-time the received data, which allows a synchronous operation to recover the transmitted signal. In optical access networks, electrical CDR or optical CDR implementations can be used. However, there are no clear guidelines or recommendations on which CDR implementation should be adopted for better performance. These missing clear recommendations are because the electrical CDR requires electronics design expertise whereas the optical CDR requires optical design expertise. Consequently, in this paper, an all-digital CDR, designed and implemented on the field-programmable gate array platform, and an optical CDR, developed by using fiber Bragg grating technology on the OptiSystem platform, are presented. Furthermore, the integration of these 2 CDR implementations with the optical access network is implemented, and their performance is evaluated for various transmission rates and communication distances. Finally, a comparative study in terms of the bit error rate between the all-digital CDR and the optical CDR is presented.

关键词： clock and data recovery fiber Bragg grating field-programmable gate array optical access network

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FPGA implementations of scale-invariant models of neural networks

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TURKISH JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES 2016年第6期24卷 5090-5099页

作者： Zhanabaev, Zeinulla Kozhagulov, Yeldos Zhexebay, Dauren al Farabi Kazakh Natl Univ Fac Phys & Technol Dept Solid State Phys & Nonlinear Phys Alma Ata Kazakhstan

Integrated circuit implementations of new models of neural networks with scale-invariant properties are presented. The specifics of such models are necessary in analysis of discrete mappings containing fractional power. We suggest an algorithm for increasing the power of a physical value by using a field-programmable gate array (FPGA). Comparisons between FPGA implementations and numerical results are demonstrated.

关键词： Neural networks field-programmable gate array digital scheme scale invariance

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HOT CHIPS 27 Introduction

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IEEE MICRO 2016年第2期36卷 6-7页

作者： Amirtharajah, Rajeevan Robatmili, Behnam Univ Calif Davis Elect & Comp Engn Dept Davis CA 95616 USA

The guest editors discuss Hot Chips 27 and the articles created for this special issue. [ABSTRACT FROM AUTHOR]

关键词： agile hardware Computer industry deep learning energy efficiency field-programmable gate array graphics high-performance computing Hot Chips instruction-set architecture machine learning makers many-core microprocessor Meetings Microprocessors multimedia Multimedia communication Operating systems programmable logic RISC-V Special issues and sections

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A comparative study of steganography designs based on multiple FPGA platforms

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INTERNATIONAL JOURNAL OF ELECTRONIC SECURITY AND DIGITAL FORENSICS 2016年第2期8卷 164-190页

作者： Mohd, Bassam J. Hayajneh, Thaier Abu Khalaf, Zaid Vasilakos, Athanasios V. Hashemite Univ Dept Comp Engn Zarqa 13115 Jordan New York Inst Technol Sch Engn & Comp Sci New York NY USA Lulea Univ Technol Dept Comp Sci Elect & Space Engn SE-93187 Skelleftea Sweden

Steganography methods conceal covert messages inside communicated data. field-programmable gate array (FPGA) hardware implementation provides speed, flexibility and configurability. It is extremely difficult to compare published results from different platforms and technologies. The goal of our research work is to mitigate the dependency by examining implementations from multiple FPGA platforms. The research studies the implementations of 12 spatial steganography methods using Altera and Xilinx FPGAs. The methods include mix-bit LSB, least significant bit (LSB), random LSB and texture-based algorithms. The objective of the research is to develop platform-independent resources, timing, power and energy models;to empower future steganography research. Further, the article evaluates steganography methods using typical performance metrics as well as a novel performance metric. The results suggest that the mix-bit methods exhibit good performance across most of the metrics. However, when image quality is a concern, the two-bit LSB is the front runner.

关键词： information security field-programmable gate array FPGA data hiding spatial steganography modelling

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Adaptive human detection approach using FPGA-based parallel architecture in reconfigurable hardware

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CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE 2017年第14期29卷

作者： Li, Yibin Gai, Keke Qiu, Meikang Dai, Wenyun Liu, Meiqin Shandong Univ Comp Sci & Engn Dept Jinan 250014 Peoples R China Pace Univ Dept Comp Sci New York NY 10038 USA Zhejiang Univ Coll Elect Engn Hangzhou 310027 ZJ Peoples R China

Currently, the rapid increment of human detections has been changing people's daily life, However, the implementation is still facing the challenges caused by the restrictions of power and hardware. The computation process results in a heavy workload even though prior researches had made efforts to reduce the complexity. We focus on this issue and propose a new approach that employs the binarization-based optimization algorithm to simplify the computation processes. Our approach is designed to minimize the necessary calculations and memory space. Moreover, we have developed the field-programmable gate array based parallel architecture to apply partial dynamic reconfiguration, which enables the remote configurations for the number of processing units. An experimental evaluation is completed in order to examine our proposed approach. According to our experimental results, the detection precision can reach a miss rate less than 1.97% and a false positive rate of 1%. The energy cost is also reduced up to 36% comparing with the prior methods. Copyright (C) 2016 John Wiley & Sons, Ltd.

关键词： binarization field-programmable gate array histogram of oriented gradients human detections

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Fundus image denoising using FPGA hardware architecture

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INTERNATIONAL JOURNAL OF COMPUTER APPLICATIONS IN TECHNOLOGY 2016年第1期54卷 1-13页

作者： Fredj, Amira Hadj Ben Abdallah, Mariem Malek, Jihene Azar, Ahmad Taher Monastir Univ Elect & Microelect Lab Monastir Tunisia Benha Univ Fac Comp & Informat Banha Egypt

Image processing algorithms, implemented in hardware, have recently emerged as the most viable solution for improving the performance of image processing systems. In this paper, a version of an anisotropic diffusion technique is used to reduce noise from retinal images, namely Speckle Reducing Anisotropic Diffusion ( SRAD). The SRAD filter can improve images corrupted by multiplicative or additive noise, but it has been the most computationally complex and it has not been suitable for software implementation in real-time processing. In this paper, an efficient field-programmable gate array ( FPGA)-based implementation of the SRAD filter is presented to accelerate the processing time. A comparison of the most used classical suppression filters like Gaussian, Median, Perona and Malik anisotropic diffusion has been carried out. The experimental results reveal a 38x performance improvement over the original MATLAB implementation and a 1.33x performance improvement over the hardware implementation using the Xilinx System Generator tool.

关键词： SRAD filter FPGA field-programmable gate array parallel architecture retinal fundus image

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