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Optimized theory-guided convolutional neural network for lung cancer classification using CT images with advanced FPGA implementation

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BIOMEDICAL SIGNAL PROCESSING AND CONTROL 2025年 106卷

作者： Manikandan, S. Karthigaikumar, P. Karpagam Coll Engn Dept Elect & Telecommun Engn Coimbatore Tamil Nadu India Karpagam Coll Engn Dept Elect & Commun Engn Coimbatore Tamil Nadu India

Lung carcinoma, commonly referred to as lung cancer is a severe disease with higher global mortality rate. The uncontrolled growth of cells in lung tissues is the reason for it. Detecting and treating lung cancer early is important for curing it, and diagnostic methods commonly include Computed Tomography (CT) scans and blood tests. However, accurately detecting and classifying pulmonary nodules in CT images remains a challenge due to the complexity of the data, higher computational demands,require for real-time processing. Existing systems often face limitations, such as high power consumption, prolonged processing times, and scalability issues, reducing their effectiveness in clinical environments. To overcome these challenges, this manuscript proposes an Optimized Theory-Guided Convolutional Neural Network for Lung Cancer Classification utilizing CT Images with Advanced FPGA Implementation (OTCNN-LCT-FPGA). Computed Tomography Image (CTI) from the LIDC-IDRI dataset are pre-processed using Variational Bayesian Robust Adaptive Filtering (VBRAF) technique, which removes noise and converts RGB images into binary format. The pre-processed images are classified as benign or malignant using Theory-Guided Convolutional Neural Network (TCNN). The Polar Coordinate Bald Eagle Search Algorithm (PBESA) is introduced to enhance the weight parameters of TCNN method while reducing resource utilization and increasing processing speed. The TCNN classifier is executed on field-programmable gate array (FPGA) to further decrease the computation time. The proposed OTCNN-LCT-FPGA method demonstrates significant improvements. How if, it achieves 6.26 %, 7.22 %, and 5.27 higher specificity and 2.96 %, 3.46 %, and 5.80 % higher F1-Score when compared to the existing methods, such as FCFNN-LCC, ISNeT-DLC-CT and DNNLCC-EOS respectively.

关键词： CT images field-programmable gate array Lung cancer Variational based Bayesian robust Adaptive Filtering Polar Coordinate Bald Eagle Search Algorithm Theory-guided Convolutional Neural Network

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Evaluating FPGA-based denoising techniques for improved signal quality in electrocardiograms

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ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING 2024年第1期120卷 93-107页

作者： Keerthiga, G. Kumar, S. Praveen Saveetha Engn Coll Dept Elect & Commun Engn Chennai Tamilnadu India

The alarming mortality rates associated with cardiac abnormalities emphasize the critical need for early and accurate detection of heart disorders to mitigate severe health consequences for patients. Electrocardiograms (ECG) are commonly employed instruments for the examination of cardiac disorders, with a preference for noise-free ECG signals to ensure precise interpretation. However, ECG signal recordings are susceptible to environmental interferences, including patient movement and electrode positioning. This paper introduces a hardware implementation for denoising ECG signals, leveraging a novel method by integrating high-order Synchrosqueezing Transform, Detrended Fluctuation Analysis, and Non-Local-Mean filter optimized by Particle Swarm Optimization (HSST-DFA-PSO-NLM) techniques on field-programmable gate array (FPGA) platforms. FPGA-based processing units are chosen for their outstanding performance attributes, including high re-programmability, speed, architectural flexibility, and low power consumption, resulting in efficient signal processing. The effectiveness of the designed filtering algorithm is evaluated using key criteria, including Signal-to-Noise Ratio (SNR) and Root Mean Square Error (RMSE) for performance assessment. Additionally, resource utilization metrics such as Look-Up Tables (LUTs), Flip Flops, and DSP Blocks, as well as power consumption measures including dynamic power and static or leakage power, are analysed across various FPGA boards (Virtex and Zedboards) utilizing the VIVADO environment. Comparative analyses are conducted to identify the most suitable FPGA board for implementation, highlighting the superior performance of the proposed design. Remarkably, the proposed denoising solution gives excellent SNR of 29.56, 29.68, and 28.86 by denoising various ECG noises. The RMSE attained by the model is also less than 0.05. This research advances the field of cardiac disorder detection by providing a reliable and efficient FPGA-based sol

关键词： Electrocardiogram Signal-to-noise ratio Denoise field-programmable gate array Zedboard Power consumption

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Research on Spaceborne Neural Network Accelerator and Its Fault Tolerance Design

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REMOTE SENSING 2025年第1期17卷 69-69页

作者： Shao, Yingzhao Wang, Junyi Han, Xiaodong Li, Yunsong Li, Yaolin Tao, Zhanpeng Xidian Univ State Key Lab Integrated Serv Networks Xian 710071 Peoples R China China Acad Space Technol Xian Xian 710100 Peoples R China Xidian Univ Sch Comp Sci & Technol Xian 710071 Peoples R China

To meet the high-reliability requirements of real-time on-orbit tasks, this paper proposes a fault-tolerant reinforcement design method for spaceborne intelligent processing algorithms based on convolutional neural networks (CNNs). This method is built on a CNN accelerator using field-programmable gate array (FPGA) technology, analyzing the impact of Single-Event Upsets (SEUs) on neural network computation. The accelerator design integrates data validation, Triple Modular Redundancy (TMR), and other techniques, optimizing a partial fault-tolerant architecture based on SEU sensitivity. This fault-tolerant architecture analyzes the hardware accelerator, parameter storage, and actual computation, employing data validation to reinforce model parameters and spatial and temporal TMR to reinforce accelerator computations. Using the ResNet18 model, fault tolerance performance tests were conducted by simulating SEUs. Compared to the prototype network, this fault-tolerant design method increases tolerance to SEU error accumulation by five times while increasing resource consumption by less than 15%, making it more suitable for spaceborne on-orbit applications than traditional fault-tolerant design approaches.

关键词： spaceborne computing single-event upset convolutional neural network field-programmable gate array fault-tolerant design

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High-speed and reduced energy delay product TCAM on FPGA for network routers

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ETRI JOURNAL 2025年第0期

作者： Vadivel, Sridhar Raj Sankara Ramapackiam, Shantha Selvakumari Mepco Schlenk Engn Coll Dept Elect & Commun Engn Sivakasi India

Ternary content-addressable memory (TCAM) is widely used in the design of high-speed search engines such as network routers and artificial-intelligence-based applications. However, traditional TCAM designs suffer from two major drawbacks. Static random access memory (RAM)-based TCAMs do one operation at a time, causing the search operation to be suspended while the update operation is in progress, rendering them unsuitable for applications with high-frequency updates. Moreover, during the implementation of wider TCAMs, when the match results are transferred from one slice to another, the last look-up table (LUT) in the slice is always set to logic one, which results in resource wastages. This research aims to overcome the problems associated with traditional TCAM design. The proposed work used six-input (RAM64X1S) LUTs in field-programmable gate arrays by allowing both search and update operations to be performed simultaneously during the data update in a particular LUT. To overcome resource wastage, the proposed design used four RAM64X1S blocks instead of RAM64M blocks. Moreover, the proposed TCAM architecture was considerably simpler, comprising LUTs with AND slicing, thus reducing FPGA resources such as slice registers and slice logic. For TCAM sizes of 512 x 36 and 1024 x 144, the slice utilization was reduced by 17% and 29%, respectively, with their speed being increased by 17% and 26%, respectively. Moreover, the lookup rate and the update rate of the designed TCAMs also improved considerably. The proposed architecture employed high-speed single-cycle searches, making it ideal for fast search applications.

关键词： data compression field-programmable gate array routers static random-access memory ternary content-addressable memory translation lookaside buffers

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Development of a proof-of-principle PET system using multi-time-over-threshold and FPGA without ADC or TDC

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NUCLEAR ENGINEERING AND TECHNOLOGY 2025年第5期57卷

作者： Kim, Kyu Bom Kim, Kyuseok Jeong, Hyun-Woo Kim, Yeonkyeong Lee, Su Hwan Yonsei Univ Coll Hlth Sci Dept Radiat Convergence Engn Wonju South Korea Eulji Univ Dept Biomed Engn Songnam South Korea Yonsei Univ Severance Hosp Dept Internal Med Div Pulm & Crit Care MedColl Med Seoul South Korea 2TS Corp 211 Hwarang Ro Seoul 08393 South Korea

The goal of this study was to extend a multi-time-over-threshold (MToT) based multi-channel front-end circuit and field-programmable gate array only data acquisition (DAQ) without analog-to-digital converter or time-todigital converter for the development of a proof-of-principle positron emission tomography (PET) system. The proposed system was configured with two detector modules, each having a 4 x 2 detector block (128 ch/detector module). The performance of the PET system using a 256-channel analog circuit and a DAQ system was evaluated by measuring energy resolution and time resolution. These values were 20 % and 1.5 ns, respectively. The calculated data packet containing energy, time, and position information was formed into 64-bit single event data package and sent to the host computer using USB 3.0 control interface. Experiment results revealed that the spatial resolution was 2.1 mm at the center and 2.2 mm at 20 mm from the center. The Derenzo Phantom based experiment showed sufficient distinguish for Hod-rod of various radius, confirming the viability of the proposed proof-of-principle system.

关键词： Multi-time-over-threshold method field-programmable gate array Analog and digital signal processing Positron emission tomography Proof-of-principle system

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A 2-Lane Discrete Multitone Wireline Receiver Datapath With Far-End Crosstalk Cancellation on RFSoC Platform

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2024年第11期71卷 4738-4742页

作者： Lee, Jaewon Jang, Seoyoung Braendli, Matthias Morf, Thomas Kossel, Marcel Francese, Pier-Andrea Kim, Gain Daegu Gyeongbuk Inst Sci & Technol Dept Elect Engn & Comp Sci Daegu 42988 South Korea IBM Res Europe Zurich Lab Dept Emerging Comp & Circuits CH-8803 Ruschlikon Switzerland

This brief presents a 2-lane discrete multitone (DMT) wireline receiver (RX) with a far-end crosstalk (FEXT) cancellation and its implementation on the ZCU111 RFSoC evaluation board for real-time functional verification. The RX datapath is implemented with the 64-parallel 128-tap multi-path delay-feedback (MDF) fast Fourier transform (FFT) to optimize resources and throughput. The multiple-input, multiple-output (MIMO) frequency-domain equalizer (FDE) compensates both channel insertion loss (IL) and FEXT based on coefficients computed from an on-chip pilot-assist channel estimation (CHEST). The platform includes a programmable logic (PL) for a DMT digital signal processor (DSP) running at 32 MHz, 2.048 GS/s data converters, and intersymbol interference (ISI)/FEXT board. This system enables the reflection of a realistic hardware impairment and real-time transceiver (TRX) operation with a quick bit error rate (BER) test. The measurement demonstrates that the MIMO DMT significantly improves a BER from 1.0E-2 to 5.8E-7 when the FEXT is canceled for a channel exhibiting 15 dB of IL and 10 dB of IL-to-crosstalk ratio (ICR) at Nyquist frequency.

关键词： MIMO communication Fast Fourier transforms Signal to noise ratio Symbols Real-time systems Loading field programmable gate arrays Serial link ADC-based serial link wireline transceiver discrete multitone DMT far-end crosstalk FEXT field-programmable gate array FPGA RFSoC

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Design of a Multiple Pseudorandom Number Generator Combined Chaotic System With RNS and Its Application to Secure Image Processing

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IEEE ACCESS 2024年 12卷 155246-155258页

作者： Liu, Chien-Chun Chen, Chih-Chiang Yan, Jun-Juh Liao, Teh-Lu Natl Cheng Kung Univ Dept Engn Sci Tainan 70101 Taiwan Air Force Inst Technol Dept Aircraft Engn Kaohsiung 82063 Taiwan Natl Cheng Kung Univ Dept Syst & Naval Mechatron Engn Tainan 70101 Taiwan Natl Chin Yi Univ Technol Dept Elect Engn Taichung 41107 Taiwan

This paper presents a novel approach to designing a multiple pseudorandom number generator (MPNG) through the integration of several key techniques. Specifically, the method leverages the chaotic dynamics of the 2D Tinkerbell system, a residue number system (RNS), and XOR operations to generate multiple sets of pseudorandom number sequences. The MPNG offers several advantages, including a simple design and low hardware resource requirements. Implemented using a field-programmable gate array (FPGA), it applies each chaotic system state to produce three sets of random number sequences, achieving a generation rate three times higher. The generated sequences are rigorously evaluated using the NIST SP800-22 and Diehard test suites, along with Shannon entropy and histogram analyses, all of which confirm their randomness. The results pass all NIST SP800-22 and Diehard test items, demonstrating the properties of random numbers. Additionally, this paper proposes a synchronization controller to achieve state synchronization between the master system and the slave system, enabling symmetric encryption and decryption applications for secure image processing.

关键词： Chaotic communication Encryption Main-secondary Generators Synchronization field programmable gate arrays NIST Hardware Noise measurement Receivers Multiple pseudorandom number generator chaotic system residue number system field-programmable gate array

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Assessment of vertical shifted carrier schemes for sinusoidal pulsewidth modulation

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JOURNAL OF POWER ELECTRONICS 2024年第11期24卷 1719-1730页

作者： Kadiyala, Bhavana Paramasivan, Muthukumar Bensraj, R. Annamalai Univ Dept Elect Engn Annamalai Nagar Chidambaram 608002 Tamil Nadu India Saveetha Inst Med & Tech Sci Saveetha Sch Engn Dept Elect & Elect Engn Chennai Tamil Nadu India

The carrier modulated sinusoidal pulsewidth modulation scheme has been acknowledged for its fundamental fortification and harmonic reduction in DC-AC conversion. This study is focused on how to get a variable output voltage with the least harmonics by changing the amplitude of the carrier wave vertically instead of modulating the reference wave (conventional SPWM). This paper proposes four control schemes for achieving the maximum fundamental voltage in a three phase voltage source inverter. The four schemes are single edge carrier shifted with (i) fixed reference and (ii) variable reference, and double edge carrier shifted with (iii) fixed reference and (iv) variable reference. In addition, the reverse modulation index and mutual modulation index are introduced as new control variables for examination. These schemes are simulated with a three phase inverter and the performance is compared with conventional sinusoidal pulsewidth modulation using MATLAB R2021. The amplitude of the fundamental voltage and the corresponding THD are reported. Digital implementations of the proposed schemes are premeditated by using VHDL language and ModelSim. The validity of the proposed schemes is experimentally investigated through a laboratory prototype of a three phase inverter module incorporated with an FPGA Spartan 6 device. This prototype is tested with a three phase induction motor as the load. The fundamental voltage and THD for the existing and proposed schemes are reported.

关键词： Reverse modulation index Mutual modulation index Voltage source inverter Pulsewidth modulation field-programmable gate array

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Software and hardware synergy for accelerated plant disease identification

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APPLIED SOFT COMPUTING 2025年 174卷

作者： Wen, Hongxing Li, Chuandong Wang, Xinpei Chen, Ling Southwest Univ Coll Elect Informat & Engn Chongqing Key Lab Nonlinear Circuits & Intelligent Chongqing 400715 Peoples R China

Plant diseases are one of the main causes of reduced crop yields. Therefore, it is necessary to adopt timely and effective identification methods and take corresponding measures. Some physical and biological detection methods have been proposed by researchers, but these methods require specialized techniques and expensive detection costs. Furthermore, the limited number of skilled technicians means that disease identification is not always timely or effective. To achieve real-time identification of plant diseases in remote areas where network and circuit are not well connected, We adopted a hardware and software co-acceleration approach to implement the design. First, we designed a lightweight convolutional neural network (CNN) and trained this network using a knowledge distillation approach. Then, we quantified the model parameters into int8 type using a method of model quantization to further compress the model size. After compression, the model size of the network is 0.035 MB and the recognition accuracy is 94.06% on the test set of the experiment. In order to deploy the proposed network on resource constrained field-programmable gate array (FPGA) devices, we used time-division multiplexing and feature map segmentation to deploy the network. Finally, our design is implemented on ZYNQ7020 with an inference speed of 35.73ms/frame and a power consumption of 1.97 W. The experimental results show that our design has the advantages of consuming less FPGA resources, low power consumption, high speed and portability. It can be used for disease recognition in multiple plant classes.

关键词： Convolutional neural network field-programmable gate array Acceleration Plant disease

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Design of an FPGA-based emulator for rapidly prototyping a nonvolatile system-on-a-chip

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JAPANESE JOURNAL OF APPLIED PHYSICS 2025年第4期64卷 04SP06-04SP06页

作者： Suzuki, Daisuke Hanyu, Takahiro Univ Aizu 90 Kami IawaseTsurugaIkki Machi Aizu Wakamatsu Fukushima 9658580 Japan Tohoku Univ 2-1-1 KatahiraAoba Ku Sendai Miyagi 9808577 Japan

This paper presents a field-programmable gate array (FPGA)-based emulator for rapidly prototyping a non-volatile (NV)-FPGA-based system on chip (SoC) where an FPGA, a central processing unit, and other peripheral modules are integrated into a single chip to address the difficulty in estimating the usefulness of an NV-FPGA-based SoC on a target system. By mimicking the NV-memory device as a sequential logic circuit, a virtual NV-FPGA SoC is implemented on a commercial FPGA board, and its system-level functional verification is performed. As a typical design example, the proposed hardware is implemented on a Digilent Basys 3 board. A fundamental arithmetic logic circuit is implemented on the NV-FPGA, and its logical behavior is the same as that of the original circuit, and NV-logic-specific functions, i.e. store and recall operations are successfully confirmed. Additionally, a 96.3% power reduction is estimated by the NV-FPGA SoC compared to that of a volatile FPGA SoC system under 1.83% of activity ratio.

关键词： field-programmable gate array nonvolatile logic hardware emulation system on a chip prototyping

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