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NUMERICAL ACCURACY AND hardware TRADEOFFS FOR CORDIC ARITHMETIC FOR SPECIAL-PURPOSE PROCESSORS

IEEE TRANSACTIONS ON COMPUTERS 1993年第7期42卷 769-779页

作者： KOTA, K CAVALLARO, JR Department of Electrical and Computer Engineering Rice University Houston TX USA

The coordinate rotation digital computer (CORDIC) algorithm is used in numerous special-purpose systems for real-time signal processing applications. It is desirable to use fixed-point CORDIC units in such systems, since the low complexity, compared to floating-point, allows multiple CORDIC units and additional hardware to be integrated on the same chip. However, an analysis of fixed-point CORDIC in the Y-reduction mode, which allows computation of the inverse tangent function, shows that unnormalized input values can result in large numerical errors. This paper describes two approaches to tackle the numerical accuracy problem. The first approach builds on a fixed-point CORDIC unit and eliminates the problem by including additional hardware for normalization. This paper presents a method to integrate the normalization operation with the CORDIC iterations for efficient implementation in O(n1.5) hardware. The second solution to the accuracy problem is to use a floating-point CORDIC unit but reduce the implementation complexity by using a hybrid architecture. We present arguments to support the use of such an architecture in certain special purpose arrays.

关键词： CORDIC ERROR ANALYSIS ERROR REDUCTION hardware complexity VLSI

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Spectrum efficiency analysis of signal alignment-based beamspace millimetre wave MIMO-NOMA systems

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IET COMMUNICATIONS 2020年第5期14卷 818-829页

作者： Salem, Ahmed Abdelaziz Benaya, A. M. El-Rabaie, Sayed Shokair, Mona Menoufia Univ Fac Elect Engn Menoufia 32952 Egypt

Non-orthogonal multiple access (NOMA) has been integrated with beamspace multi-input multi-output (MIMO) to enhance system spectrum efficiency (SE) by serving more than one user per dedicated radio frequency (RF) chain. However, balancing the system performance with significant RF reduction is still challenging. In this study, the authors propose beamspace MIMO-NOMA system based on signal alignment (SA) concept, where they will be able to tackle the issue of hardware complexity with a significant performance. Spectrum and energy efficiencies are analysed through two main stages. First, the excess degrees-of-freedom of beamspace MIMO-NOMA are exploited by SA to suppress the inter-beam/pair interference through designing user detection vectors and precoding matrix. Accordingly, a significant RF-chains reduction is provided. Second, power allocation coefficients are evaluated upon the optimal SE in order to mitigate intra-beam/pair interference. Moreover, the authors derive a tight closed formula for optimal SE based on Karush-Kuhn-Tucker analysis, which is validated by a heuristic-based optimal solution. Simulation results show a superior performance gain over orthogonal multiple access technique. Furthermore, the Monte-Carlo numerical solution depicts the marginal performance gap between the analytical and heuristic-based optimisation approach. This confirms the accuracy and rigidity of the proposed system.

关键词： optimisation antenna arrays MIMO communication precoding Monte Carlo methods spectrum efficiency analysis signal alignment-based beamspace MIMO-NOMA systems beamspace concept millimetre wave multiinput multioutput hardware complexity required radio frequency chains system capacity RF chains user numbers nonorthogonal multiple access system spectrum efficiency dedicated RF chain system performance RF reduction authors propose beamspace MIMO-NOMA signal alignment concept energy efficiencies excess degrees-of-freedom user detection vectors precoding matrix significant RF-chains reduction optimal SE Karush-Kuhn-Tucker analysis heuristic-based optimal solution superior performance gain orthogonal multiple access technique marginal performance gap analytical based optimisation approach heuristic-based optimisation approach

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BUILT-IN TESTING OF MEMORY USING AN ON-CHIP COMPACT TESTING SCHEME

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IEEE TRANSACTIONS ON COMPUTERS 1986年第10期35卷 862-870页

作者： KINOSHITA, K SALUJA, KK UNIV NEWCASTLE DEPT ELECT & COMP ENGNNEWCASTLENSW 2308AUSTRALIA

In this paper we study the problem of testing RAM. A new fault model, which encompasses the existing fault models, is proposed. We then propose a scheme of testing faults from the new fault model using built-in testing techniques. We introduce concept of p-hard and determine the complexity of the extra hardware required for built-in self-testing on our hardness scale. A novel approach using microcoded ROM for implementation of built-in testing is also proposed and its complexity is determined.

关键词： Weight Sensitive Faults Built In Self Testing BIST Built In Testing BIT hardware complexity Pattern Sensitive Faults Random Access Memory RAM Stuck At Faults

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Performance of low level protocols in high traffic wireless body sensor networks

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PEER-TO-PEER NETWORKING AND APPLICATIONS 2020年第3期13卷 850-871页

作者： Boudargham, Nadine Abdo, Jacques Bou Demerjian, Jacques Guyeux, Christophe Makhoul, Abdallah Notre Dame Univ Fac Engn Deir El Kamar Lebanon Notre Dame Univ Fac Nat & Appl Sci Deir El Kamar Lebanon Lebanese Univ Fac Sci LaRRIS Fanar Lebanon Univ Bourgogne Franche Comte CNRS FEMTO ST Inst Belfort France

The rapid development of medical sensors has increased the interest in Wireless Body Area Network (WBAN) applications where physiological data from the human body and its environment is gathered, monitored, and analyzed to take the proper measures. In WBANs, it is essential to design MAC protocols that ensure adequate performance and Quality of Service (QoS). This paper investigates Medium Access Control (MAC) protocols used in WBAN, and compares their performance in a high traffic environment with respect to different QoS and network performance metrics. Such scenario can be induced in case of emergency for example, where physiological data collected from all sensors on human body should be sent simultaneously to take appropriate action. This study can also be extended to cover collaborative WBAN systems where information from different bodies is sent simultaneously leading to high traffic. OPNET simulations are performed to compare the performance of the different MAC protocols under the same experimental conditions. A new MAC scheme aiming to enhance the delay, throughput, and energy performance of the system is then proposed and compared to existing protocols, to evaluate its performance in high traffic environment.

关键词： WBAN Static-TDMA Dynamic-TDMA FDMA CSMA CA DS-CDMA Delay Scalability Throughput Probability of collision Time synchronization hardware complexity Energy OPNET

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Memory Access Scheduling Based on Dynamic Multilevel Priority in Shared DRAM Systems

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ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION 2016年第4期13卷 1–26页

作者： Xiong, Dongliang Huang, Kai Jiang, Xiaowen Yan, Xiaolang Zhejiang Univ Inst VLSI Design Hangzhou Zhejiang Peoples R China

Interapplication interference at shared main memory severely degrades performance and increasing DRAM frequency calls for simple memory schedulers. Previous memory schedulers employ a per-application ranking scheme for high system performance or a per-group ranking scheme for low hardware cost, but few provide a balance. We propose DMPS, a memory scheduler based on dynamic multilevel priority. First, DMPS uses "memory occupancy" to measure interference quantitatively. Second, DMPS groups applications, favors latency-sensitive groups, and dynamically prioritizes applications by employing a per-level ranking scheme. The simulation results show that DMPS has 7.2% better system performance and 22% better fairness over FRFCFS at low hardware complexity and cost.

关键词： Memory access scheduling hardware complexity memory occupancy dynamic multilevel priority group

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New demodulation filter in digital phase rotation beamforming

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ULTRASONICS 2006年第3期44卷 265-271页

作者： Schneider, Fabio Kurt Yoo, Yang Mo Agarwal, Anup Koh, Liang Mong Kim, Yongmin Univ Washington Dept Elect Engn Image Comp Syst Lab Seattle WA 98195 USA Univ Washington Dept Bioengn Image Comp Syst Lab Seattle WA 98195 USA Nanyang Technol Univ Sch Elect & Elect Engn Singapore 639798 Singapore

In this paper, we present a new quadrature demodulation filter to reduce hardware complexity in digital phase rotation beamforming. Due to its low sensitivity to phase delay errors, digital quadrature demodulation is commonly used in ultrasound machines. However, since it requires two lowpass filters for each channel to remove harmonics, the direct use of conventional finite impulse response (FIR) filters in ultrasound machines is computationally expensive and burdensome. In our new method, an efficient multi-stage uniform coefficient (MSUC) filter is utilized to remove harmonic components in phase rotation beamforming. In comparison with the directly implemented FIR (DI-FIR) and the previously-proposed signed-power-of-two FIR (SPOT-FIR) lowpass filters, the proposed MSUC filter reduces the necessary hardware resources by 93.9% and 83.9%, respectively. In simulation, the MSUC filter shows a negligible degradation in image quality. The proposed method resulted in comparable spatial and contrast resolution to the DI-FIR approach in the phantom tom study. These preliminary results indicate that the proposed quadrature demodulation filtering method could significantly reduce the hardware complexity in phase rotation beamforming while maintaining comparable image quality. (c) 2006 Elsevier B.V. All rights reserved.

关键词： ultrasonic imaging beamforming phase rotation beamforming quadrature demodulation filter hardware complexity

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Taxonomy and Performance Evaluation of Hybrid Beamforming for 5G and Beyond Systems

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IEEE ACCESS 2020年 8卷 74605-74626页

作者： Rihan, Mohamed Soliman, Tarek Abed Xu, Chen Huang, Lei Dessouky, Moawad, I Shenzhen Univ Sch Math & Stat Shenzhen 518060 Peoples R China Shenzhen Univ Sch Elect & Informat Engn Shenzhen 518060 Peoples R China Menoufia Univ Fac Elect Engn Dept Elect & Commun Engn Menoufia 21974 Egypt

Increasing demand for higher data-rate wireless connectivity with lower latency is fueling the explorations of millimeter-wave (mmWave) spectrum and massive MIMO communications. Both technologies are recognized as the key enablers of 5G and beyond 5G (B5G) networks. Hybrid beamforming is one of the most promising energy and cost-effective approaches to realize mmWave massive MIMO communications with lower complexity and smaller training overhead. With the motivation of giving more insights and in-deep technical recommendations to B5G network designers regarding hybrid beamforming, we present a hybrid beamforming taxonomy in terms of channel state information (CSI) availability, frequency bandwidth, architecture complexity, analog beamformer components, number of users, connectivity to RF chains, and the digital and analog beamforming design. Furthermore, we provide a comprehensive survey on the state-of-the-art use-cases for each classification followed by identification of the future challenges and open research issues.

关键词： Hybrid beamforming (HBF) energy efficiency (EE) millimeter wave (mmWave) hardware complexity massive-MIMO analog beamforming (ABF) and digital beamforming (DBF)

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Approximate expressions for BER performance in downlink mmWave MU-MIMO hybrid systems with different data detection approaches

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IET COMMUNICATIONS 2020年第14期14卷 2223-2230页

作者： Ortega, Alvaro Javier Sampaio-Neto, Raimundo David, Rodrigo Pereira Pontifical Catholic Univ Rio De Janeiro PUC Rio Ctr Studies Telecommun CETUC 225 Gavea Rio De Janeiro Brazil Brazilian Inst Metrol INMETRO Lab Telecommun Rua Santa Alexandrina416 Rio Comprido Rio De Janeiro Brazil

Millimetre-wave (mmWave) communications have been regarded as a key technology for the next-generation cellular systems since the huge available bandwidth can potentially provide the rates of multiple gigabits per second. Conventional precoding and combining techniques are impractical at mmWave scenarios due to manufacturing costs and power consumption. Hybrid alternatives have been considered as a promising technology to provide a compromise between hardware complexity and system performance. This study examines, using a semi-analytic approach, the downlink performance of massive MU-MIMO mmWave systems in terms of the bit error rate (BER). Also, a general expression is derived to estimate an upper bound/approximation to the BER performance via the Monte Carlo method, which can be used for any hybrid precoder/combiner, modulation and different data detectors. Numerical results evidence that the approximate BER expressions provide values very close to the ones obtained through simulation using only two statistical moments related to parameters of the system, mean and variance.

关键词： Monte Carlo methods cellular radio MIMO communication error statistics precoding millimetre wave communication next generation networks approximation theory power consumption hardware complexity semianalytic approach massive MU-MIMO mmWave systems bit error rate BER performance approximate BER expressions downlink mmWave MU-MIMO hybrid systems data detection millimetre-wave communications next-generation cellular systems combining techniques precoding techniques Monte Carlo method hybrid precoder-combiner statistical moments

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0.0045 mm² 15.8 μW three-stage amplifier driving 10x-wide (0.15-1.5 nF) capacitive loads with >50° phase margin

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ELECTRONICS LETTERS 2015年第6期51卷 454-455页

作者： Yan, Zushu Mak, Pui-In Law, Man-Kay Martins, Rui Paulo Univ Macau State Key Lab Analog & Mixed Signal VLSI Taipa Peoples R China Univ Macau Fac Sci & Technol ECE Taipa Peoples R China

A three-stage amplifier employing embedded capacitor-multiplier compensation (ECMC) and active parallel compensation (APC) to enhance the area efficiency when driving nF-range capacitive loads (C-L) is presented. Unlike the conventional current-buffer Miller compensation, ECMC applied to the dominant compensation path saves substantial power and area, while securing a large gain-band-idth product. The created left-half-plane zero also benefits the phase margin (PM). For the APC, unlike the traditional passive parallel compensation, this work benefits from the Miller effect to avoid the area-consuming resistor, and reduces the entailed capacitances without lowering the parasitic pole position. A multi-path G(m)-boosting second stage enhances the effective transconductance and DC gain. With 0.0045 mm(2) of area and 15.8 mu W of power, the 0.18 mu m CMOS three-stage amplifier measures 1.13 MHz unity-gain frequency, 0.41 V/mu s average slew rate and 56.2 degrees PM at 1 nF C-L. Stable responses with >50 degrees PM are attained for a 10 x range of C-L from 0.15 to 1.5 nF. The achieved figure-of-merit accounting for both die area and power compares favourably with the state of the art.

关键词： biomedical ultrasonics FIR filters frequency response biomedical electronics generalised dynamic decimation method ultrasound imaging focused echo signal finite impulse response filter frequency response programmable rational factor polyphase multiplier-accumulators power consumption hardware complexity

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NEW hardware ARCHITECTURE FOR FAST RASTER IMAGE GENERATION

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ELECTRONICS LETTERS 1988年第7期24卷 382-383页

作者： KIM, SS EO, KS KYUNG, CM Department of Electrical Engineering KAIST Seoul Korea

We describe a new hardware architecture known as an edge painting tree (EPT) using pipelined binary trees for fast generation of scanline images for raster scan graphics. The hardware complexity of EPT is much smaller than that of earlier raster graphics engines owing to the use of 1 bit logic rather than log2P bit logic where P is the number of pixels per scanline.

关键词： Computer architecture hardware complexity EPT raster scan graphics 1 bit logic hardware architecture Terminals and graphic displays image processing computer architecture surface modelling Optical information, image and video signal processing edge painting tree computerised picture processing increased speed Computer vision and image processing techniques pipelined binary trees computer graphic equipment fast generation of scanline images solid modelling raster scan display fast raster image generation reduced hardware complexity

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