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DESIGN AND ANALYSIS OF A LARGE-SCALE MULTICAST OUTPUT BUFFERED ATM SWITCH

IEEE-ACM TRANSACTIONS ON NETWORKING 1995年第2期3卷 126-138页

作者： CHAO, HJ CHOE, BS MYONGJI UNIV DEPT ELECT ENGNYONGINSOUTH KOREA

We propose and analyze a recursive modular architecture for implementing a large-scale multicast output buffered ATM switch (MOBAS), A multicast knockout principle, an extension of the generalized knockout principle, is applied in constructing the MOBAS in order to reduce the hardware complexity (e.g., the number of switch elements and interconnection wires) by almost one order of magnitude, In our proposed switch architecture, four major functions of designing a multicast switch: cell replication, cell routing, cell contention resolution, and cell addressing, are all performed distributively so that a large switch size is achievable. The architecture of the MOBAS has a regular and uniform structure and, thus, has the advantages of: 1) easy expansion due to the modular structure, 2) high integration density for VLSI implementation, 3) relaxed synchronization for data and clock signals, and 4) building the center switch fabric (i.e., the multicast grouping network) with a single type of chip, A two-stage structure of the multicast output buffered ATM switch (MOBAS) is described, The performance of the switch fabric in cell loss probability is analyzed, and the numerical results are shown, We show that a switch designed to meet the performance requirement for unicast calls will also satisfy multicast calls' performance, A 16 x 16 ATM crosspoint switch chip based on the proposed architecture has been implemented using CMOS 2-mu m technology and tested to operate correctly.

关键词： Telecommunication Network Routing Asynchronous Transfer Mode Electronic Switching Systems VLSI CMOS Digital Integrated Circuits Network Topology Buffer Storage Communication complexity Packet Switching Synchronisation Microprocessor Chips Large Scale Multicast Output Buffered ATM Switch Recursive Modular Architecture MOBAS Multicast Knockout Principle hardware complexity CMOS 2 Spl Mu M Technology 16 Spl Times 16 ATM Crosspoint Switch Chip Cell Replication Cell Routing Cell Contention Resolution Cell Addressing Expansion Modular Structure Integration Density VLSI Synchronization Data Signal Clock Signal Center Switch Fabric Two Stage Structure Performance Cell Loss Probability 2 Micron Large Scale Systems Switches Asynchronous Transfer Mode Fabrics CMOS Technology hardware Wires Routing Very Large Scale Integration Synchronization

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The implementation of the clustered-OFDM-based transceiver on an FPGA device: A comprehensive comparison

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IET COMMUNICATIONS 2021年第6期15卷 824-839页

作者： de Campos, Fabricio P. V. Sirimarco, Lucas M. de Campos, Marcello L. R. Ribeiro, Moises V. Fed Univ Juiz de Fora UFJF Dept Elect Engn Juiz De Fora Brazil Fed Univ Rio de Janeiro UFRJ Program Elect Engn Rio De Janeiro Brazil

Aiming at reducing hardware complexity and power consumption of multicarrier-based broadband transceivers, this contribution discusses and analyzes the implementation of clustered-orthogonal frequency division multiplexing (OFDM)-based transceiver in a field programmable gate array (FPGA) device. In this sense, several OFDM schemes covering baseband and passband data communications are implemented. The hardware resource utilization and power consumption related to each scheme, after being implemented in the FPGA device, are discussed and compared. Numerical results show that the OFDM scheme based on P(center dot)-II and Q(center dot)-III, which is a modified version of the hermitian symmetric (HS)-OFDM scheme, which performs both baseband and passband data communications, demands the lowest hardware resource utilization and power consumption, reducing to 1/3 the hardware resource utilization. As a result, P(center dot)-II and Q(center dot)-III constitute an interesting candidate for implementing new generations of high data rate, low hardware resource utilization, and low-power consumption clustered-OFDM-based transceivers for broadband data communication. Last but not least, numerical results show that the controllers used to integrate all components of a clustered-OFDM-based transceiver can demand sizeable hardware resource utilization and power consumption and, therefore, they have to be carefully designed.

关键词： clustered-OFDM-based transceiver carrier transmission on power lines low-power consumption Logic circuits clustered-orthogonal frequency division multiplexing-based transceiver passband data communications hermitian symmetric-OFDM scheme field programmable gate array device hardware complexity Modulation and coding methods broadband networks OFDM modulation broadband data communication field programmable gate arrays baseband data communications lowest hardware resource utilization radio transceivers sizeable hardware resource utilization data communication Power line systems low hardware resource utilization Radio links and equipment FPGA device

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Design of non-uniform filter bank transmultiplexer with canonical signed digit filter coefficients

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IET SIGNAL PROCESSING 2009年第3期3卷 211-220页

作者： Manoj, V. J. Elizabeth, E. NIT Dept Elect & Commun Engn Calicut Kerala India

Design of non-uniform filter bank transmultiplexer (NUFB TMUX) with canonical signed digit (CSD) coefficients is presented. NUFB TMUX is preferred in a multicarrier communication system when applications with different data rates are to be multiplexed. If the. filter coefficients are represented in CSD format, the hardware complexity of the NUFB TMUX can be reduced. A continuous coefficient NUFB TMUX is designed and the coefficients of the. filters are synthesised in CSD format using genetic algorithm (GA). Separate objective functions are formulated for the fitness evaluation of the. filters. Chromosomes are encoded as ternary digit strings. New crossover and mutation techniques are introduced to preserve the canonical property of the signed power of two (SPT) representations. For the fast convergence of the GA, position-dependent probability of mutation is used. Simulation results show that the CSD coefficient NUFB TMUX designed using the proposed algorithm has better signal-to-interference ratio (SIR) than that of continuous coefficient NUFB TMUX and CSD coefficient NUFB TMUX obtained by rounding. Frequency responses of its. filters are better than that of the. filters in CSD coefficient NUFB TMUX obtained by rounding and comparable with that of continuous coefficient NUFB TMUX.

关键词： transmultiplexing General circuit analysis and synthesis methods position-dependent mutation probability Optimisation techniques circuit complexity hardware complexity probability canonical signed digit filter coefficients channel bank filters signal-to-interference ratio multicarrier communication system Filters and other networks signed power-of-two representations nonuniform filter bank transmultiplexer mutation techniques genetic algorithm crossover technique continuous coefficient genetic algorithms filter coefficients Other topics in statistics

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Design of narrow transition band variable bandwidth digital filter

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IET CIRCUITS DEVICES & SYSTEMS 2020年第6期14卷 750-757页

作者： Roy, Subhabrata Chandra, Abhijit Jadavpur Univ Dept Instrumentat & Elect Engn Kolkata 700106 India

This study presents a novel implementation technique for linear phase variable bandwidth finite impulse response (FIR) filters with a noticeable reduction in transition bandwidth as well as hardware complexity. In this proposition, concept of Farrow structure based design technique is effectively utilised;whereas the fixed sub-filters are constructed from a generalised interpolated bandpass method based low-pass FIR filter by means of different techniques such as interpolation, up-sampling and masking. Simulation results have shown the frequency response characteristics of several variable bandwidth FIR filters, designed with the help of the proposed architecture. Simulation results have shown a drastic reduction of transition bandwidth resulting from the proposed variable bandwidth FIR filters of up to similar to 70-80%, when compared with other state-of-the-art filtering techniques, with a significant reduction in hardware complexity of up to similar to 50%.

关键词： FIR filters frequency response digital filters interpolation low-pass filters fixed sub-filters generalised interpolated bandpass method low-pass FIR filter variable bandwidth FIR filters transition bandwidth state-of-the-art filtering techniques hardware complexity narrow transition band Farrow structure based design technique frequency response characteristics finite impulse response linear phase variable bandwidth variable bandwidth digital filter

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Improved convergent distributed arithmetic based low complexity pipelined least-mean-square filter

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IET CIRCUITS DEVICES & SYSTEMS 2018年第6期12卷 792-801页

作者： Khan, Mohd Tasleem Shaik, Rafi Ahamed Matcha, Surya Prakash Indian Inst Technol Guwahati Dept Elect & Elect Engn Gauhati India

This study presents an improved convergent distributed arithmetic (DA)-based low complexity pipelined least-mean-square filter. The concept is based on a convex combination of two adaptive filters (ADFs) where the convergence performance of the combined filter is adjusted by the step-sizes of ADFs. The proposed technique replaced two ADF units by a single unit of the DA-based ADF. Further reduction in hardware complexity is achieved by sharing the filter partial products. Moreover, a bit-level coefficient update unit is employed to minimise its hardware complexity. In addition, a novel low-cost strategy is presented to improve the convergence performance of the proposed filter by comparing the time-window corresponding to the maximum correlation of delayed error signals Compared with the best existing scheme, the proposed design offers 46.42% fewer adders, 36.69% fewer registers and 18.75% fewer multiplexers for a 64th-order filter. Application specific integrated circuit synthesis results show that the proposed design occupies 37.10% less chip-area and consumes 24.79% less power. In addition, the proposed design provides 20.35% less area-delay-product and 4.76% less energy-per-sample for 64th order with the fourth-order base unit over the best existing scheme.

关键词： application specific integrated circuits low-power electronics adaptive filters integrated circuit design distributed arithmetic least mean squares methods convergent distributed arithmetic least-mean-square filter convex combination adaptive filters combined filter ADF units hardware complexity filter partial products 64th-order filter fourth-order base unit application specific integrated circuit synthesis

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Maximising capacity of MIMO systems with receive antenna subarray formation

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ELECTRONICS LETTERS 2008年第20期44卷 1204-1206页

作者： Theofilakos, P. Kanatas, A. G. Univ Piraeus Dept Digital Syst Wireless Commun Lab GR-18534 Athens Greece

Antenna subarray formation is a novel RF pre-processing technique that reduces hardware complexity of multiple-input multiple-output systems while alleviating the performance degradation of conventional antenna selection techniques. With this method, each RF chain is allocated to a lineal combination of the responses of a subset of the available antenna elements, which is performed in the radio frequency domain. A novel. analytical. suboptimal algorithm is introduced for antenna subarray formation based on instantaneous channel information that maximises the effective channel capacity.

关键词： receive antenna subarray formation performance degradation maximising capacity MIMO systems antenna accessories multiple-input multiple-output systems antenna arrays conventional antenna selection techniques RF preprocessing technique radio frequency domain channel capacity hardware complexity antenna elements Antenna accessories Antenna arrays instantaneous channel information Radio links and equipment receiving antennas

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Accuracy controlled iterative method for efficient sigmoid function approximation

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ELECTRONICS LETTERS 2020年第18期56卷 914-916页

作者： Chiluveru, S. R. Tripathy, M. Mohapatra, B. Indian Inst Technol Roorkee Dept Elect Engn Roorkee Uttar Pradesh India

The sigmoid activation function plays an essential role in implementing neural networks in hardware. However, due to a high degree of non-linearity, the hardware implementation of the activation function itself is a daunting job. In this Letter, the authors proposed an accuracy controlled iterative algorithm for the piecewise linear approximation of the sigmoid function. The proposed algorithm approximates sigmoid activation with an optimised number of linear functions for a given error. The accuracy and hardware complexity of the resulting approximation function are compared with the state-of-the-art literature.

关键词： iterative methods function approximation piecewise linear techniques neural nets optimisation hardware implementation daunting job piecewise linear approximation linear functions hardware complexity accuracy controlled iterative method sigmoid function approximation sigmoid activation function neural networks

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Multiplicative repetition-based spinal codes with low computational complexity

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IET COMMUNICATIONS 2017年第17期11卷 2660-2666页

作者： Chen, Peiyao Bai, Baoming Li, Qiong Zhang, Rui Xidian Univ State Key Lab Integrated Serv Networks Xian Shaanxi Peoples R China

Spinal codes, a new class of rateless codes, have received considerable attention for their capacity-approaching performance over noisy channels. Hash function is the core of a spinal encoder to generate infinite coded symbols, which has higher hardware complexity. In this study, the authors propose a multiplicative repetition-based method instead of the hash function to generate innumerable symbols with low encoding complexity. Furthermore, both frozen-aided and cyclic redundancy check-aided decoding methods are proposed to improve the spectral efficiency. Simulation results show that the proposed spinal codes have lower computational complexity and can achieve higher spectral efficiency in the high signal-to-noise ratio region compared with the conventional ones over both additive white Gaussian noise and Rayleigh fading channels.

关键词： cyclic redundancy check codes hash function hardware complexity multiplicative repetition capacity-approaching performance infinite coded symbols noisy channels frozen-aided decoding computational complexity encoding complexity cyclic redundancy check decoding signal-to-noise ratio spinal codes spinal encoder decoding spectral efficiency rateless codes Codes

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Joint beamforming with low-resolution PSs for millimetre-wave communications

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ELECTRONICS LETTERS 2016年第18期52卷 1541-1542页

作者： Dong, Yue Chen, Chen Jin, Ye Peking Univ State Key Lab Adv Opt Commun Syst & Networks Beijing Peoples R China

An iterative joint beamforming algorithm taking the low-resolution phase shifters (PSs) into account is proposed for millimetre-wave communications. Furthermore, performance degradation incurred by the low-resolution PSs is analysed. Simulation results show that the proposed algorithm can achieve comparable performance with the existing alternatives in terms of the array gains and convergence rates but with limited hardware cost. Thus, the proposed scheme can be an acceptable tradeoff between the performance and hardware complexity.

关键词： array signal processing iterative methods millimetre wave phase shifters convergence of numerical methods computational complexity hardware complexity performance complexity convergence rates array gains performance degradation millimetre-wave communications low-resolution phase shifters low-resolution PS iterative joint beamforming algorithm

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CONVOLUTION ALGORITHMS FOR SMALL-WORD-LENGTH DIGITAL-FILTERING APPLICATIONS

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IEE JOURNAL ON ELECTRONIC CIRCUITS AND SYSTEMS 1979年第6期3卷 253-256页

作者： REDDY, NS REDDY, VU Radar and Communication Centre Indian Institute of Technology Kharagpur India

Implementation of rectangular transforms (r.t.) in modular arithmetic and computation of number theoretic transforms through Winograd's algorithm are discussed. The computational effort of various algorithms to implement real convolution is investigated. Considering the signal/noise ratio performance and hardware complexity, it is shown that the r.t.s are best suited for digital-filtering applications with word lengths less than about 16 bits. Finally, r.t.s are shown to be the most amenable to the application of the Chinese remainder theorem for increasing the dynamic range

关键词： Chinese remainder theorem transforms rectangular transforms Winograd's algorithm real convolution signal/noise ratio performance Other numerical methods Digital arithmetic methods computational requirements digital arithmetic digital convolution convolution algorithms number theoretic transforms Digital filters digital filters hardware complexity small word length digital filtering modular arithmetic

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