Power hardware-in-the-loop (PHIL) simulation combines the advantages of digital simulation and physical experiment, which provides great convenience for research and verification of a complex electric system, such as ...
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Power hardware-in-the-loop (PHIL) simulation combines the advantages of digital simulation and physical experiment, which provides great convenience for research and verification of a complex electric system, such as the high-voltage direct current (HVdc) system. The digital interface algorithm realizes interconnection of the digital and physical system, but it is also the main factor to affect stability and accuracy of the PHIL results. In this article, the damping impedance interface algorithm is adopted to test the performance of a modular multilevel converter (MMC) connected into an HVdc system. Instead of online acquiring the exact MMC dc impedance, a simple RLC damping impedance is proposed to ensure stability and particularly, low-frequency accuracy for the PHIL system. Moreover, as testing in the laboratory does not allow hundreds of MVA-rated physical MMC, suitable scaling factors are proposed to design a scaled-down MMC prototype which presents identical dynamic characteristic with a full-scale MMC. A PHIL setup including RT-LAB real-time simulator, power amplifier, and a scaled-down MMC prototype is built and the experiments confirm the effectiveness of the proposed interface algorithm.
The interface algorithm is critical for accuracy of the real-time integration simulation system of renewable energy and the power grid. To improve the overall performance of the existing interface algorithms, this pap...
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The interface algorithm is critical for accuracy of the real-time integration simulation system of renewable energy and the power grid. To improve the overall performance of the existing interface algorithms, this paper proposes an optimized interface algorithm based on the auxiliary damping impedance method interface current feedback. We explain in detail the implementation principle of the new interface algorithm and the calculation method of impedance matching and also provide a parallel timing control logic. Using the new interface algorithm, we derive equations for voltage and current of the digital simulation system side and the device under test side and also compare it with the naturally coupled system without interface delay. Finally, we verify the accuracy of the new interface algorithm via establishing a complete model of the real-time integration simulation system with a wind turbine and the power grid. The results show that the accuracy can be improved 95% in the digital simulation system side and 17% in the device under test side by using the proposed interface algorithm in this paper.
Connection of two digital real-time simulators introduces some delay that is not present in a real network. This delay has to be accounted for by using an interface algorithm. The paper presents two interface algorith...
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Connection of two digital real-time simulators introduces some delay that is not present in a real network. This delay has to be accounted for by using an interface algorithm. The paper presents two interface algorithms for real-time digital simulations and proposes a method for the selection of the most appropriate one for a specific case. The first algorithm is the Ideal Transformer Model (ITM) algorithm which is a straightforward method that does not affect the system impedance characteristic. However, using certain ratio of the network and load impedance may to some extent result in an unstable operation of the coupled simulators system. In order to cope with this deficiency, the Transmission Line Model (TLM) algorithm is used as the second algorithm. In this way, the system stability is achieved. Compared to the ITM algorithm, the TLM algorithm accuracy is lower meaning that the interface algorithm should be selected depending on the system configuration. A method for choosing the most viable algorithm is proposed and cases of using the two algorithms are presented.
With the increase of the number and capacity of HVDC, the influence of HVDC system on AC power network is more and more complex. Electromechanical transient simulation and electromagnetic transient simulation cannot m...
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ISBN:
(纸本)9781467371063
With the increase of the number and capacity of HVDC, the influence of HVDC system on AC power network is more and more complex. Electromechanical transient simulation and electromagnetic transient simulation cannot meet the requirements of HVDC system study in large power grid. Therefore, research on power system electromechanical-electromagnetic hybrid simulation has very important significance. In this paper, we improve the algorithm of the interface based on the PSD-PSModel hybrid simulation. The optimization curve fitting algorithm based on FFT is proposed to improve the accuracy of the algorithm. The test method of interface algorithm is proposed, and the practical conclusion of PSD-PSModel interface is obtained.
The Power-Hardware-in-the-Loop (PHIL) methodology enables testbed solutions that support the development of complex mechatronic components. In PHIL testing, a unit under test (UUT) is coupled with a virtual representa...
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The Power-Hardware-in-the-Loop (PHIL) methodology enables testbed solutions that support the development of complex mechatronic components. In PHIL testing, a unit under test (UUT) is coupled with a virtual representation of its surroundings. As an example, a real railway pantograph current collector UUT can be tested in real-time interaction with a virtual overhead catenary. However, due to the closed-loop feedback interconnection and the exchange of power between real and virtual systems, such a PHIL control structure is highly sensitive to time delays in the signal paths which limits its performance, accuracy, and stability. In this work, methods to evaluate and compensate for the effect of time delays in a typical PHIL structure are proposed. A model-based PHIL control system is introduced to demonstrate the effect of time-delay compensation techniques, including utilising specific reduced-order models to achieve efficient time-delay compensation. The performance of the control system is demonstrated and validated via simulations and experiments on a scaled PHIL test setup, which is related to railway pantograph testing. In addition, criteria to analyse system stability are formulated and demonstrated with respect to uncompensated time delays and unknown UUT contact stiffness.
Developing a general and stable numerical interface for power hardware-in-the-loop (PHIL) applications is a major challenge. This paper proposes a stable, robust and precise implementation of a multi-time-step interfa...
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Developing a general and stable numerical interface for power hardware-in-the-loop (PHIL) applications is a major challenge. This paper proposes a stable, robust and precise implementation of a multi-time-step interface for a PHIL simulator based on the Bergeron transmission line model (BTLM). Two limitations of the transmission-line-based interface were identified, and remedial strategies were formulated in order to ensure that the interface was compatible with the PHIL application. Stability and passivity analyses were then conducted on the resulting interface to verify its performance. The proposed interface was implemented in an experimental 3-kVA PHIL setup, using a custom-made switching power amplifier (PA). Multiple tests were performed in order to demonstrate the stability and accuracy of the closed-loop system under a wide range of operating conditions and with various devices under test (DUTs). Experimental results were obtained from islanding tests involving different simulated load configurations and solar inverter responses to network disturbance while operating in a closed-loop configuration.
The simulation of microgrids requires increasingly advanced tools to take into account phenomena with different time scales and at the same time integrate real devices. This last aspect is of great interest in the sci...
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ISBN:
(纸本)9781728170190
The simulation of microgrids requires increasingly advanced tools to take into account phenomena with different time scales and at the same time integrate real devices. This last aspect is of great interest in the scientific community for the possibility of testing control algorithms and system performance. In this article is proposed a new Hardware In the Loop (HIL) simulation framework, which integrates the potential of an industrial embedded controller, that can be programmed with Model Based Design (MBD) techniques, along with the computing capacity of a Real-Time (RT) simulator dedicated to the simulation of power grids. The framework is applied to the simulation of a microgrid that includes several Distributed Energy Resources (DER), highlighting the problems of integration.
Power Hardware-in-the-Loop (PHiL) becomes more and more an important part at the investigation of dynamics and stability issues of the electrical grids. As derived from Hardware-in-the-Loop (HiL) approach, one of the ...
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ISBN:
(纸本)9781728110783
Power Hardware-in-the-Loop (PHiL) becomes more and more an important part at the investigation of dynamics and stability issues of the electrical grids. As derived from Hardware-in-the-Loop (HiL) approach, one of the central PHiL requirements is to feedback measurement signals into the simulation. In PHIL applications, the operational behavior of a connected device is integrated within real-time simulations. With the integration of the Hardware under Test (HuT) into a PHiL test bench, stability issues may arise. Therefore, this paper focuses on the stability investigation and the description of typical PHiL setup and condititions. The frequency domain modelling reveals phenomenon of instability as well as concepts of interface algorithm (IA) and Compensation Methods (CM). To investigate the behavior of different devices as HuT, also the HuT is modelled and simulated in the real time environment. In the next step, the analog loopback integrates HuT models into PHiL simulation by using HYPERSIM from OPAL-RT as simulation software (time domain). Analog loopback introduces time delay into the PHiL simulation that would also occur in real PHiL applications with connected devices to build a more realistic environment. The simulation with analog loopback consists of implemented IAs which feedback operational behavior of HuT models into PHiL test bench. In selected simulation approaches, the mentioned technique loops back currents of various loads and inverters. Therefore it is possible to evaluate the feedback of devices with different described methods and their impact on stability and signal fidelity.
This thesis presents an in-detail stability analysis of a Power Hardware in the Loop (PHIL) network formed through an Ideal Transformer Method (ITM) interface. The ever-growing demand for PHIL testing necessitates tho...
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This thesis presents an in-detail stability analysis of a Power Hardware in the Loop (PHIL) network formed through an Ideal Transformer Method (ITM) interface. The ever-growing demand for PHIL testing necessitates thorough research in the area. The ITM interface devices are crucial in determining the accurate and stable PHIL. Therefore, this thesis considers the parameters of these individual devices to develop analytical equations with which the stability can be determined quantitatively. This helps in choosing the interface devices as well as the system parameters before forming the PHIL setup. The PHIL testing is something that requires an experimental result to validate its operation besides the theoretical and mathematical formulations. The work in this thesis follows the methodology of mathematical analysis followed by experimental results. The PHIL setup used in this thesis for its analysis considers a simple resistor divider network to formulate its hypothesis and finally extends the study to evaluate a Grid-Connected PV Inverter (GCPI) in a PHIL architecture. The delay present in the PHIL network as a result of non-ideal interface devices creates a major discrepancy between the results in the actual system with the PHIL system. In order to eliminate the effect of this delay, this thesis considers the application of a Smith Predictor (SP) compensator. This SP compensator consists of a model of the interface and the estimation of the delay in the PHIL network of choice. This thesis works towards developing the model of the interface device in the ITM interface. To validate the model, an experimental gain and phase measurements are made and compared with the gain and phase of the model. This ensures that an accurate model of the interface is obtained to model the SP compensator. Also, the round-trip delay of the PHIL network under study is estimated through various combinations of I/O devices. Once the SP compensator model is developed, it is implemented in Re
This paper presents a systematic approach to characterize the stability of a power-hardware-in-the-loop (PHIL) platform, an important step in PHIL tests. Many existing works focus the stability assessments on the PHIL...
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ISBN:
(纸本)9781728103952
This paper presents a systematic approach to characterize the stability of a power-hardware-in-the-loop (PHIL) platform, an important step in PHIL tests. Many existing works focus the stability assessments on the PHIL interface algorithm;however, this work considers all software and hardware subsystems that form the closed loop of the PHIL experiment and develops a complete closed-loop stability assessment. This assessment is developed in the context of a common framework that can be readily applied to other PHIL platforms. This paper presents methods for characterizing key PHIL subsystems toward obtaining transfer functions to be used for analysis. The systematic stability assessment approach is demonstrated for a case study involving PHIL testing of a solar inverter and validated using experimental data.
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