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CHALLENGE OF MTJ-BASED NONVOLATILE logic-in-memory architecture FOR DARK-SILICON logic LSI

SPIN 2013年第4期3卷 1340014页

作者： Hanyu, Takahiro Tohoku Univ Elect Commun Res Inst Aoba Ku 2-1-1 Katahira Sendai Miyagi 9808577 Japan

This paper presents an architecture-level approach, called nonvolatile logic-in-memory (NV-LIM) architecture, to solving performance-wall and power-wall problems in the present CMOS-onlybased logic-LSI (Large-Scaled Integration) processors. The use of magnetic tunnel junction devices combined with a CMOS-gate style makes it possible to achieve a high-performance and ultra-low-power logic LSI. Some concrete examples using the proposed method allow you to achieve the desired performance improvement compared to a corresponding CMOS-only-based realization.

关键词： logic-in-memory architecture magnetic tunnel junction logic LSI magneto-resistive random access memory (MRAM)

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Fine-Grained Power-Gating Scheme of a Nonvolatile logic-in-memory Circuit for Low-Power Motion-Vector Extraction

Fine-Grained Power-Gating Scheme of a Nonvolatile Logic-in-M...

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10th IEEE International New Circuits and Systems Conference (NEWCAS)

作者： Sihotang, Magdalena Matsunaga, Shoun Hanyu, Takahiro Tohoku Univ Elect Commun Res Inst Sendai Miyagi 9808577 Japan Tohoku Univ Ctr Spintron Integrated Syst Sendai Miyagi 9808577 Japan

ISBN: (纸本)9781467308595

Data-transfer localization is a key technique to solve communication bottleneck between memory and logic modules in realizing high-speed VLSI systems, while it is difficult to use power-gating technique because volatile storage functions are distributed in a CMOS logic-circuit plane, which causes large power dissipation. In this paper, we utilize nonvolatile logic-in-memory (NV-LIM) architecture, where nonvolatile storage functions are distributed over a logic-circuit plane, to solve the above issues. As a typical example of the NV-LIM circuit, we apply it to motion-vector extraction. By the use of fine-grained power-gating technique, total power dissipation of the proposed hardware can be reduced to 60% in comparison with that of a conventional CMOS-only-based hardware.

关键词： component MRAM spintronics image compression fine-grained pipelining logic-in-memory architecture sum-of-absolute-difference operation

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Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing

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PROCEEDINGS OF THE IEEE 2016年第10期104卷 1844-1863页

作者： Hanyu, Takahiro Endoh, Tetsuo Suzuki, Daisuke Koike, Hiroki Ma, Yitao Onizawa, Naoya Natsui, Masanori Ikeda, Shoji Ohno, Hideo Tohoku Univ Elect Commun Res Inst Sendai Miyagi 9807577 Japan Tohoku Univ Ctr Spintron Integrated Syst Sendai Miyagi 9808577 Japan Tohoku Univ Ctr Innovat Integrated Elect Syst Sendai Miyagi 9800845 Japan Tohoku Univ Grad Sch Engn Sendai Miyagi 9808579 Japan Tohoku Univ Frontier Res Inst Interdisciplinary Sci Sendai Miyagi 9808578 Japan

Nonvolatile spintronic devices have potential advantages, such as fast read/write and high endurance together with back-end-of-the-line compatibility, which offers the possibility of constructing not only stand-alone RAMs and embedded RAMs that can be used in conventional VLSI circuits and systems but also standby-power-free high-performance nonvolatile CMOS logic employing logic-in-memory architecture. The advantages of employing spintronic devices, especially magnetic tunnel junction (MTJ) devices with CMOS circuits, are discussed, and the current status of the MTJ-based VLSI computing paradigm is presented along with its prospects and remaining challenges.

关键词： Field-programmable gate array image recognition logic-in-memory architecture magneto-resistive RAM microcontroller unit (MCU) MTJ device MTJ/MOS-hybrid circuit nonvolatile LSI power gating standby power ternary content-addressable memory

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NV-Clustering: Normally-Off Computing Using Non-Volatile Datapaths

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IEEE TRANSACTIONS ON COMPUTERS 2018年第7期67卷 949-959页

作者： Roohi, Arman DeMara, Ronald F. Univ Cent Florida Dept Elect Engn & Comp Sci Orlando FL 32816 USA

With technology downscaling, static power dissipation presents a crucial challenge to multicore, many-core, and System-on-Chip (SoC) architectures due to the increased role of leakage currents in overall energy consumption and the need to support power-gating schemes. Herein, a non-Volatile (NV) flip-flop design approach, referred to as NV Clustering, is developed to realize middleware-transparent intermittent computing. First, a logic-Embedded Flip-Flop (LE-FF) is developed to realize rudimentary Boolean logic functions along with an inherent state-holding capability within a compact footprint. Second, the NV-Clustering synthesis procedure and corresponding tool module are utilized to instantiate the LE-FF library cells within conventional Register Transfer Language (RTL) specifications. This selectively clusters together logic and NV state-holding functionality, based on energy and area minimization criteria. NV-Clustering is applied to a wide range of benchmarks including ISCAS-89, MCNS, and ITC-99 computational circuits using a LE-FF based on the Spin Hall Effect (SHE)-assisted Spin Transfer Torque (STT) Magnetic Tunnel Junction (MTJ). Simulation results validate functionality and power dissipation, area, and delay benefits. For instance, results for ISCAS-89 benchmarks indicate 15 percent area reduction on average, up to 22 percent reduction in energy consumption, and up to 14 percent reduction in delay as compared to alternative NV-FF based designs, as evaluated via SPICE simulation at the 45-nm technology node.

关键词： Non-volatile computing architecture normally-off computation logic-in-memory architecture memory-in-logic datapath non-volatile flip-flop non-volatile logic spin-transfer torque (STT) switching energy-sparing computation

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Reliability-Enhanced Hybrid CMOS/MTJ logic Circuit architecture

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IEEE TRANSACTIONS ON MAGNETICS 2017年第11期53卷 1-5页

作者： Zhang, Deming Zeng, Lang Zhang, Youguang Klein, Jacques Olivier Zhao, Weisheng Beihang Univ Fert Beijing Inst BDBC Beijing 100191 Peoples R China Beihang Univ Sch Elect & Informat Engn Beijing 100191 Peoples R China Univ Paris Sud Ctr Nanosci & Nanotechnol F-91405 Orsay France

Benefitting from its non-volatility, nearly infinite endurance, good scalability, and great CMOS compatibility, magnetic tunnel junction (MTJ) embedded in conventional CMOS logic circuits has been proposed as one potentially powerful solution to introduce non-volatility in today's programmable logic circuits, which is envisioned to achieve low power and high area efficiency. However, the recently proposed hybrid CMOS/MTJ logic circuits and prototypes based on such a logic-in-memory architecture suffers from a severe reliability issue, which is the precise transformation from MTJ resistance to electric signals due to its limited tunnel magnetoresistance ratio (TMR <= 150%), i.e., the requirement of nearly zero sensing error for logic applications. In this paper, to overcome this sensing reliability issue, a novel sense amplifier (SA) with high sensing margin is proposed for such hybrid CMOS/MTJ logic circuit architecture. By using a commercial CMOS 40 nm design kit and a physics-based MTJ compact model, hybrid CMOS/MTJ transient and Monte Carlo statistic simulations have been conducted to demonstrate the functionality of the proposed SA and evaluate its performance, respectively.

关键词： Hybrid CMOS/MTJ logic circuits logic-in-memory architecture magnetic tunnel junction (MTJ) non-volatility sensing reliability

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A high-speed and low-voltage associative co-processor with exact Hamming/Manhattan-distance estimation using word-parallel and hierarchical search architecture

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 2004年第8期39卷 1383-1387页

作者： Oike, Y Ikeda, M Asada, K Univ Tokyo Tokyo 1138656 Japan

A high-speed and low-voltage associative co-processor with exact Hamming or Manhattan distance estimation is presented. The word-parallel and hierarchical search architecture is achieved using a logic-in-memory digital implementation. In the bit-serial search architecture, it is important to shorten the search cycle time since the total search time generally increases in proportion to the bit length. The present hierarchical architecture achieves a high-speed operation with a large input number. Furthermore, it provides a result for the data close to the input with a fewer number of clocks. Therefore, it reduces the number of clocks required for nearest-match detection in practical use. The circuit implementation allows unlimited database capacity and achieves a low-voltage operation under 1.0 V for system-on-a-chip applications. The capacity scalability makes it easy to compute a function of Manhattan distance estimation using thermometer encoding. A 64-bit 32-word associative co-processor has been designed using a one-poly-Si five-metal 0.18-mum CMOS process and has been successfully tested. The measurement results show that the operation achieves a speed of 411.5 MHz at a supply voltage of 1.8 V. The worst-case search time is 158.0 ns for a 64-bit 32-word database. In a low-voltage operation, the operation speed achieves 40.0 MHz at a supply voltage of 0.75 V.

关键词： associative co-processor content addressable memory (CAM) Hamming distance hierarchical search logic-in-memory architecture Manhattan distance word parallel

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Energy Efficient In-memory AES Encryption Based on Nonvolatile Domain-wall Nanowire

Energy Efficient In-Memory AES Encryption Based on Nonvolati...

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Design, Automation and Test in Europe Conference and Exhibition (DATE)

作者： Wang, Yuhao Yu, Hao Sylvester, Dennis Kong, Pingfan Nanyang Technol Univ Sch Elect & Elect Engn Singapore 639798 Singapore Univ Michigan Dept Elect Engn & Comp Sci Ann Arbor MI 48109 USA

ISBN: (纸本)9783981537024

The widely applied Advanced Encryption Standard (AES) encryption algorithm is critical in secure big-data storage. Data oriented applications have imposed high throughput and low power, i.e., energy efficiency (J/bit), requirements when applying AES encryption. This paper explores an in-memory AES encryption using the newly introduced domain-wall nanowire. We show that all AES operations can be fully mapped to a logic-in-memory architecture by non-volatile domain-wall nanowire, called DW-AES. The experimental results show that DW-AES can achieve the best energy efficiency of 24 pJ/bit, which is 9X and 6.5X times better than CMOS ASIC and memristive CMOL implementations, respectively. Under the same area budget, the proposed DW-AES exhibits 6.4X higher throughput and 29% power saving compared to a CMOS ASIC implementation;1.7X higher throughput and 74% power reduction compared to a memristive CMOL implementation.

关键词： cryptography low-power electronics nanowires random-access storage Advanced Encryption Standard CMOS ASIC implementations DW-AES data oriented applications energy efficient in-memory AES encryption logic-in-memory architecture low power memristive CMOL implementations nonvolatile domain-wall nanowire secure big-data storage Application specific integrated circuits CMOS integrated circuits Ciphers Encryption Nanoscale devices Nonvolatile memory Throughput

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IRC: Cross-layer design exploration of Intermittent Robust Computation units for IoTs 18

IRC: Cross-layer design exploration of Intermittent Robust C...

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18th IEEE-Computer-Society Annual Symposium on VLSI (ISVLSI)

作者： Roohi, Arman DeMara, Ronald F. Univ Cent Florida Elect & Comp Engn Dept Orlando FL 32816 USA

ISBN: (纸本)9781728133911

Energy-harvesting-powered computing offers intriguing and vast opportunities to dramatically transform the landscape of the Internet of Things (IoT) devices by utilizing ambient sources of energy to achieve battery-free computing. In order to operate within the restricted energy capacity and intermittency profile, it is proposed to innovate Intermittent Robust Computation (IRC) Unit as a new duty-cycle-variable computing approach leveraging the non-volatility inherent in spin-based switching devices. The foundations of IRC will be advanced from the device-level upwards, by extending a Spin Hall Effect Magnetic Tunnel Junction (SHE-MTJ) device. The device will then be used to realize SHE-MTJ Majority/Polymorphic Gate (MG/PG) logic approaches and libraries. Then a logic-Embedded Flip-Flop (LE-FF) is developed to realize rudimentary Boolean logic functions along with an inherent state-holding capability within a compact footprint. Finally, the NV-Clustering synthesis procedure and corresponding tool module are proposed to instantiate the LE-FF library cells within conventional Register Transfer Language (RTL) specifications. This selectively clusters together logic and NV state-holding functionality, based on energy and area minimization criteria. It also realizes middleware-coherent, intermittent computation without checkpointing, micro tasking, or software bloat and energy overheads vital to IoT. Simulation results for various benchmark circuits including ISCAS-89 validate functionality and power dissipation, area, and delay benefits.

关键词： Non-volatile memory logic-in-memory architecture non-volatile flip-flop magnetic tunnel junction (MTJ)

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Normally-off computing design methodology using spintronics: from device to architectures 11

Normally-off computing design methodology using spintronics:...

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11th International Green and Sustainable Computing Workshop (IGSC)

作者： Roohi, Arman Univ Nebraska Dept Comp Sci & Engn Intelligent Device Applicat iDEA Lab 2 Lincoln NE 68588 USA

ISBN: (纸本)9781665415521

This work shows a promising solution to efficiently implement normally-off computing (NoC) and power analysis side-channel attack resilient designs using spin-based devices. Spintronics, as post-CMOS devices, provide interesting features such as non-volatility, which plays an essential role in NoC structures. Besides, spin-based components can naturally function as a polymorphic gate (PG) that realizes reconfigurable logic functions with inherent security attributes. However, Spintronics' utilization imposes power and area overhead compared to CMOS-based designs. Thus, herein an efficient design methodology is introduced to mitigate these overheads. This approach is first extended to realize the targeted insertion PG Modules within the VLSI implementations to make it resilient against power failure, entitled NV-Clustering. Then PARC as an extension of NV-Clustering was developed as a power-masked synthesis method in the presence of power analysis side-channel attack. PARC randomly generates power maskable building blocks with the optimum PDP and area overhead. In addition to NV-Clustering, the PARC can be expanded against fault injection approaches due to PG modules' reconfigurability to cover the faults.

关键词： Non-volatile memory logic-in-memory architecture non-volatile flip-flop magnetic tunnel junction (MTJ)

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Magnetic Tunnel Junction for Nonvolatile CMOS logic

Magnetic Tunnel Junction for Nonvolatile CMOS Logic

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International Electron Devices Meeting (IEDM)

作者： Ohno, Hideo Endoh, Tetsuo Hanyu, Takahiro Kasai, Naoki Ikeda, Shoji Tohoku Univ Ctr Spintron Integrated Syst Aoba Ku Sendai Miyagi 9808577 Japan

ISBN: (纸本)9781424474196

Magnetic tunnel junction (MTJ) device, a nonvolatile spintronic device, is capable of fast-read/write with high endurance together with back-end-of-the-line (BEOL) compatibility, offering a possibility of constructing not only stand-alone RAMs and embedded RAMs that can be used in conventional VLSI circuits and systems but also low-power high-performance nonvolatile CMOS logic employing logic-in-memory architecture. The advantages of employing MTJs with CMOS circuits are discussed and the current status of the MTJ technology is presented along with its prospect and remaining challenges.

关键词： BEOL compatibility CMOS logic circuits MTJ device RAM back-end-of-the-line compatibility logic-in-memory architecture magnetic tunnel junction magnetic tunnelling magnetoelectronics nonvolatile CMOS logic nonvolatile spintronic device random-access storag

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