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MICROPROCESSING AND MICROPROGRAMMING 1983年第5期12卷 285-290页

作者： KAMINSKA, B ZABRODZKI, J CEMI INST ELECTRON TECHNOLWARSAWPOLAND WARSAW TECH UNIV INST INFORMATPL-00665 WARSAWPOLAND

We show how the concept of proper operation region can be used for the purpose of integrated circuit testing. The testing methodology proposed was practically verified using the 8080A microprocessor as an example. The paper presents the regions of proper operation VDD(VBB), VDD(VBB) and VDD(TDI) obtained for 8080A microprocessors supplied by different manufacturers (AMD, Intel, NS). The results obtained indicate that not all microprocessors can operate correctly within the admissible parameter ranges specified by the technical data. These results also indicate the essential differences between the products supplied by different manufacturers.

关键词： Integrated Circuit testing Proper Operation Region microprocessor testing Digital IC testing

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Evolving assembly programs:: How games help microprocessor validation

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IEEE TRANSACTIONS ON EVOLUTIONARY COMPUTATION 2005年第6期9卷 695-706页

作者： Corno, F Sánchez, E Squillero, G Politecn Torino DAUIN I-10129 Turin Italy

Core War is a game where two or more programs, called warriors, are executed in the same memory area by a time-sharing processor. The final goal of each warrior is to crash the others by overwriting them with illegal instructions. The game was popularized by A. K. Dewdney in his Scientific American column in the mid-1980s. In order to automatically devise strong warriors, mu GP, a test program generation algorithm, was extended with the ability to assimilate existing code and to detect clones;furthermore, a new selection mechanism for promoting diversity independent from fitness calculations was added. The evolved warriors are the first machine-written programs ever able to become King of the Hill (champion) in all four main international Tiny Hills. This paper shows how playing Core War may help generate effective test programs for validation and test of microprocessors. Tackling a more mundane problem, the described techniques are currently being exploited for the automatic completion and refinement of existing test programs. Preliminary experimental results are reported.

关键词： automatic programming Core War evolutionary program generation games microprocessor testing

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Hybrid-SBST methodology for efficient testing of processor cores

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IEEE DESIGN & TEST OF COMPUTERS 2008年第1期25卷 64-75页

作者： Kranitis, Nektarios Merentitis, Andreas Theodorou, George Paschalis, Antonis Gizopoulos, Dimitris Univ Athens Dept Informat & Telecommun Athens 15784 Greece Univ Piraeus Dept Informat Piraeus Greece

Because of their complexity and various architectural features, today's commercial processor cores limit the effectiveness of a single test methodology. However, self-test programs based on deterministic software-based self-test (SBST) methodologies combined with verification-based self-test programs and supplemented by directed random test-program generation prove very effective as a test strategy.

关键词： microprocessor testing Functional testing Software Based Self Test H SBST Computer Architecture ATPG RTPG

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Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2005年第11期13卷 1296-1304页

作者： Chatterjee, B Sachdev, M Univ Waterloo Dept Elect & Comp Engn Waterloo ON N2L 3G1 Canada Intel Corp Chandler AZ 85226 USA

In this paper, we present the design of a 32-b arithmetic and log unit (ALU) that allows low-power operation while supporting a design-for-test (DFT) scheme for delay-fault testability. The low-power techniques allow for 18% reduction in ALU total energy for 180-nm bulk CMOS technology with minimal performance degradation. In addition, there is a 22% reduction in standby mode leakage power and 23% lower peak current demand. In the test mode, we employ a built-in DFT scheme that can detect delay faults while reducing the test-mode automatic test equipment clock frequency.

关键词： design for testability digital circuits flip-flops microprocessor testing very large scale integration (VLSI)

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MIHST: A Hardware Technique for Embedded microprocessor Functional On-Line Self-Test

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IEEE TRANSACTIONS ON COMPUTERS 2014年第11期63卷 2760-2771页

作者： Bernardi, Paolo Ciganda, Lyl Mercedes Sanchez, Ernesto Reorda, Matteo Sonza Politecn Torino Dipartimento Automat & Informat I-10129 Turin Italy

testing processor cores embedded in systems-on-chip (SoCs) is a major concern for industry nowadays. In this paper, we describe a novel solution which merges the SBST and BIST principles. The technique we propose forces the processor to execute a compact SBST-like test sequence by using a hardware module called microprocessor Hardware Self-Test (MIHST) unit, which is intended to be connected to the system bus like a normal memory core, requesting no modification of the processor core internal structure. The benefit of using the MIHST approach is manifold: while guaranteeing the same or higher defect coverage of the traditional SBST approach, it reduces the time for test execution, better preserves the processor core Intellectual Property (IP), does not require the system memory to store the test program nor the test data, and can be easily adopted for non-concurrent on-line testing, since it minimizes the required system resources. The feasibility and effectiveness of the approach were evaluated on a couple of pipelined processors.

关键词： microprocessor testing SBST functional testing on-line testing

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testing for function and performance:: Towards an integrated processor validation methodology

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JOURNAL OF ELECTRONIC testing-THEORY AND APPLICATIONS 2000年第1-2期16卷 29-48页

作者： Bose, P IBM Corp Thomas J Watson Res Ctr Yorktown Hts NY 10598 USA

microprocessor design teams use a combination of simulation-based and formal verification techniques to validate the pre-silicon models prior to "tape-out" and chip fabrication. Pseudo-random test case generation to "cover" the architectural space is still relied upon as the principal means to identify design bugs. However, such methods are limited to functional bugs only. Detection and diagnosis of timing (performance) bugs at the architectural level is largely an expert job. Architects guide the performance team to run manually generated test cases to validate the design from a performance viewpoint. In this paper, we will review some of the new approaches being tried out to automate the generation of performance test cases. We will show how this can be done within the basic framework of current functional validation and testing of pre-silicon processor models. Three categories of "reference" specifications are used in determining the defect-free pipeline timing behavior associated with generated test cases: (a) axiomatic specifications of intrinsic machine latencies and bandwidths;(b) proven analytical models for simple basic block and loop test cases;and, (c) a stable reference behavioral/functional (pre-RTL) model of the processor under development. We report experimental results obtained in performance validation studies applied to real PowerPC (TM) processor development projects.

关键词： microprocessor testing performance test cases test generation bounds modeling performance validation integrated methodology

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Software-Based Self-Test of Set-Associative Cache Memories

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IEEE TRANSACTIONS ON COMPUTERS 2011年第7期60卷 1030-1044页

作者： Di Carlo, Stefano Prinetto, Paolo Savino, Alessandro Politecn Torino Control & Comp Engn Dept I-10129 Turin Italy

Embedded microprocessor cache memories suffer from limited observability and controllability creating problems during in-system tests. This paper presents a procedure to transform traditional march tests into software-based self-test programs for set-associative cache memories with LRU replacement. Among all the different cache blocks in a microprocessor, testing instruction caches represents a major challenge due to limitations in two areas: 1) test patterns which must be composed of valid instruction opcodes and 2) test result observability: the results can only be observed through the results of executed instructions. For these reasons, the proposed methodology will concentrate on the implementation of test programs for instruction caches. The main contribution of this work lies in the possibility of applying state-of-the-art memory test algorithms to embedded cache memories without introducing any hardware or performance overheads and guaranteeing the detection of typical faults arising in nanometer CMOS technologies.

关键词： Memory testing microprocessor testing cache memories software-based self-test

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Alpha 21164 manufacturing test development and coverage analysis

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IEEE DESIGN & TEST OF COMPUTERS 1998年第3期15卷 98-104页

作者： Stolicny, CJ Davies, R McKernan, P Truong, T Compaq Comp Corp Shrewsbury MA 01545 USA

To meet the challenge of creating test vectors for the Alpha 21164 microprocessor, Compaq's engineers describe ct test generation and grading scheme that solves time-to-market, quality, and cost concerns.

关键词： Alpha 21164 Manufacturing Test microprocessor testing Fault Coverage Design For Test DFT

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Synthesis of an 8051-like micro-controller tolerant to transient faults

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JOURNAL OF ELECTRONIC testing-THEORY AND APPLICATIONS 2001年第2期17卷 149-161页

作者： Cota, É Lima, F Rezgui, S Carro, L Velazco, R Lubaszewski, M Reis, R Univ Fed Rio Grande do Sul PPGC Inst Informat BR-91501970 Porto Alegre RS Brazil TIMA Lab F-38031 Grenoble France Univ Fed Rio Grande do Sul DELET BR-90035190 Porto Alegre RS Brazil

This paper presents the implementation of a fault detection and correction technique used to design a robust 8051 micro-controller with respect to a particular transient fault called Single Event Upset (SEU). A specific study regarding the effects of a SEU in the micro-controller behavior was performed. Furthermore, a fault tolerant technique was implemented in a version of the 8051. The VHDL description of the fault-tolerant microprocessor was prototyped in a FPGA environment and results in terms of area overhead, level of protection and performance penalties are discussed.

关键词： integrated circuits radiation effects aerospace testing built-in-testing microprocessor testing

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Extensible environment for test program generation for microprocessors

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PROGRAMMING AND COMPUTER SOFTWARE 2014年第1期40卷 1-9页

作者： Kamkin, A. S. Sergeeva, T. I. Smolov, S. A. Tatarnikov, A. D. Chupilko, M. M. Russian Acad Sci Inst Syst Programming Moscow 109004 Russia

Development of test programs and analysis of the results of their execution is the basic approach to verification of microprocessors at the system level. There is a variety of methods for the automation of test generation, starting with the generation of random code and ending with directed model-based test generation. However, there is no cure-all method. In practice, combinations of various complementary techniques are used. Unfortunately, no solution for the integration of various test generation methods into a unified environment is currently available. To test a microprocessor, verification engineers are forced to use many different test generators, which results in a number of difficulties, such as (1) the necessity to ensure the compatibility of tool configurations (in each tool, a specific description of the target microprocessor is used, which leads to duplication of information);(2) the necessity to develop utilities for integration tools (different tools have different interfaces and use different data formats). This paper describes a concept of extensible environment for test program generation for microprocessors. This environment provides a unified approach for test generation;it supports widespread test generation techniques, and can be extended by new testing tools. The proposed concept was partially implemented in MicroTESK (microprocessor T Esting and Specification Kit).

关键词： microprocessor programming microprocessor testing COMPUTERS testing TEST generators AUTOMOTIVE electronics COMPILERS (Computer programs) COMPUTER software

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