Silicon (Si) waveguide crossing serves as an enabling technology for dense Si photonic integrated circuits. Efficient crossing designs significantly boost the performance of photonic devices with many crossings. In th...
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Silicon (Si) waveguide crossing serves as an enabling technology for dense Si photonic integrated circuits. Efficient crossing designs significantly boost the performance of photonic devices with many crossings. In this paper, several fundamental optical logic functions, such as XOR, AND, OR, NOT, NOR, NAND, and XNOR, are reported at 1550 nm telecom wavelength using direct Si waveguide crossing. The proposed scheme is made up of three input waveguides and one output waveguide arranged in the shape of the symbol ' + ' with a microring resonator in the middle. The operation of the specified logicfunctions depends on the constructive and destructive interferences generated by the phase differences between the incident optical beams. Using the contrast ratio and amplitude modulation metrics, the performance of the target logic operations is evaluated. Additionally, it is investigated and assessed how much the critical operating parameters affect the spectrum transmission. The proposed waveguide-based scheme can achieve better performance compared to other reported designs of similar nature, according to simulation outcomes derived using Lumerical FDTD.
Graphdiyne(GDY)is emerging as a promising material for various applications owing to its unique structure and fascinating ***,the application of GDY in electronics and optoelectronics are still in its infancy,primaril...
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Graphdiyne(GDY)is emerging as a promising material for various applications owing to its unique structure and fascinating ***,the application of GDY in electronics and optoelectronics are still in its infancy,primarily owing to the huge challenge in the synthesis of large-area and uniform GDY film for scalable *** a modified van der Waals epitaxy strategy is proposed to synthesize wafer-scale GDY film with high uniformity and controllable thickness directly on graphene(Gr)surface,providing an ideal platform to construct large-scale GDY/Gr-based optoelectronic synapse *** synaptic behaviors have been realized,and the linear and symmetric conductance-update characteristics facilitate the implementation of neuromorphic computing for image recognition with high accuracy and strong fault *** functions including“NAND”and“NOR”are integrated into the synapse which can be executed in an optical ***,a visible information sensing-memory-processing system is constructed to execute real-time image acquisition,in situ image memorization and distinction tasks,avoiding the time latency and energy consumption caused by data conversion and transmission in conventional visual *** results highlight the potential of GDY in applications of neuromorphic computing and artificial visual systems.
Optoelectronic synapses integrating synaptic and optical-sensing functions exhibit large advantages in neuromorphic computing for visual information processing and complex learning, recognition, and memory in an energ...
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Optoelectronic synapses integrating synaptic and optical-sensing functions exhibit large advantages in neuromorphic computing for visual information processing and complex learning, recognition, and memory in an energy-efficient way. However, electric stimulation is still essential for existing optoelectronic synapses to realize bidirectional weight-updating, restricting the processing speed, bandwidth, and integration density of the devices. Herein, a two-terminal optical synapse based on a wafer-scale pyrenyl graphdiyne/graphene/PbS quantum dot heterostructure is proposed that can emulate both the excitatory and inhibitory synaptic behaviors in an optical pathway. The simple device architecture and low-dimensional features of the heterostructure endow the optical synapse with robust flexibility for wearable electronics. This optical synapse features a linear and symmetric conductance-update trajectory with numerous conductance states and low noise, which facilitates the demonstration of accurate and effective pattern recognition with a strong fault-tolerant capability even at bending states. A series of logicfunctions and associative learning capabilities have been demonstrated by the optical synapses in optical pathways, significantly enhancing the information processing capability for neuromorphic computing. Moreover, an integrated visible information sensing memory processing system based on the optical synapse array is constructed to perform real-time detection, in situ image memorization, and distinction tasks. This work is an important step toward the development of optogenetics-inspired neuromorphic computing and adaptive parallel processing networks for wearable electronics.
Recently, the need for optical signal processing with high information capacity and low cost is rapidly increasing while Boolean functions handled by single-function logic gates are very limited and high cost. Therefo...
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Recently, the need for optical signal processing with high information capacity and low cost is rapidly increasing while Boolean functions handled by single-function logic gates are very limited and high cost. Therefore, we overcome the single-function limitation by investigating through means of theoretical analysis the performance of all-optical multifunctional six basic logic gates, AND, NOR, XOR, OR, XNOR, and NAND, for the first time using the nonlinearity properties of cross-phase modulation in a single compact scheme based on few semiconductor optical amplifiers (SOAs) at a data rate of 100 Gb/s acceptable. The AND and XOR logic gates are performed using SOAs-assisted Mach-Zehnder interferometers while the NOR logic gate is performed using a single SOA followed by a delayed interferometer. Then three additional logic gates, OR, XNOR, and NAND, are performed by the combination of the outcomes of the AND, XOR, and NOR logic gates. The performance of the considered functions is evaluated by three metrics, i.e. quality factor, extinction ratio, and contrast ratio. The achieved results confirm that six basic logicfunctions can be executed with acceptable performance using the proposed compact scheme at 100 Gb/s.
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