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Lithium-Ion Battery State of Health Estimation Based on Feature Reconstruction and Transformer-GRU parallel architecture

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ENERGIES 2025年第5期18卷 1236-1236页

作者： Chen, Bing Zhang, Yongjun Wu, Jinsong Yuan, Hongyuan Guo, Fang South China Univ Technol Sch Elect Power Guangzhou 510641 Peoples R China Guangdong Teway Energy Storage Technol Co Ltd China Energy Engn Grp Guangzhou 510660 Peoples R China Foshan Univ Sch Mechatron Engn & Automat Foshan 528200 Peoples R China

Estimating the state of health of lithium-ion batteries in energy storage systems is a key step in their subsequent safety monitoring and energy optimization management. This study proposes a method for estimating the state of health of lithium-ion batteries based on feature reconstruction and Transformer-GRU parallel architecture to solve the problems of noisy feature data and the poor applicability of a single model to different types and operating conditions of batteries. First, the incremental capacity curve was constructed based on the charging data, smoothed using Gaussian filtering, and the diverse health features were extracted in combination with the charging voltage curve. Then, this study used the CEEMDAN algorithm to reconstruct the IC curve features, which reduces noisy data due to the process of data collection and processing. Lastly, this study used the cross-attention mechanism to fuse the Transformer and GRU neural networks, which constructed a Transformer-GRU parallel model to improve its ability to mine time-dependent features and global features for state of health estimation. This study conducted experiments using three datasets from Oxford, CALCE, and NASA. The results show that the RMSE of the state of health estimation by the proposed method is 0.0071, which is an improvement of 61.41% in the accuracy of its baseline model.

关键词： lithium-ion battery state of health feature reconstruction data-driven Transformer-GRU parallel architecture

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A decentralized optimization framework for multi-MGs in distribution network considering parallel architecture

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INTERNATIONAL JOURNAL OF ELECTRICAL POWER & ENERGY SYSTEMS 2025年 164卷

作者： Jiang, Dengyin Zhou, Xiaoqian Ai, Qian Hou, Yuanjun Zhao, Yuan Shanghai Dianji Univ Sch Elect Engn Shanghai 201306 Peoples R China Shanghai Jiao Tong Univ Sch Elect Engn Shanghai 200240 Peoples R China Shanghai Dayu Informat Technol Co Ltd Shanghai 201615 Peoples R China Univ Iceland Elect Power Syst Lab EPS Lab Reykjavik Iceland

In view of centralized optimization facing the shortcomings of heavy communication burden, poor privacy, lack of autonomy or susceptibility to communication failures, a decentralized optimization framework is proposed to apply in parallel architecture particularly constituted by multi-microgrids (MMGs) in a distribution network based on accelerated analytical target cascading (ATC). Accelerated ATC algorithm can be applied to perform decentralized optimization in a sequential manner between distribution network agents and microgrid agents in a faster convergence speed compared with the traditional ATC algorithm. In order to ensure the stability of power flow and to incorporate unit commitment into the problem, a comprehensive economic dispatch model in the form of mixed-integer second-order cone programming (MISOCP) is developed and integrated into decentralized optimization framework. In our proposed decentralized optimization framework, each agent only needs to exchange a small amount of boundary information with its neighboring agents to find the feasible solutions without revealing their private operational information. The novelty of this work includes (1) the application and acceleration of the ATC algorithm in the proposed decentralized optimization framework;(2) the extensive investigation of the solution feasibility of the derived MISOCP problem for various penalty multipliers, scales and objective functions. Three types of microgrids (MGs) for residential, industry and business sectors are connected to the distribution network in parallel, respectively. Aiming at MMGs constructed by three MGs and six MGs in the distribution network, the proposed decentralized optimization framework is validated for the acceleration of ATC algorithm, varying penalty multipliers as well as different types of objective functions in terms of the feasibility of distributed solutions. Case studies based on the modified IEEE 33-bus distribution network are conducted to show the e

关键词： Decentralized optimization MMGs Accelerated analytical target cascading parallel architecture

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parallel architecture for 2-D discrete wavelet transform with low energy consumption

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IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 2008年第8期E91A卷 2068-2075页

作者： Ishihara, Nozomi Abe, Koki Univ Electrocommun Dept Comp Sci Chofu Tokyo 1828585 Japan NEC Corp Ltd Syst IP Core Labs Kawasaki Kanagawa 2118666 Japan

A novel two-dimensional discrete wavelet transform (2-DDWT) parallel architecture for higher throughput and lower energy consumption is proposed. The proposed architecture fully exploits full-page burst accesses of DRAM and minimizes the number of DRAM activate and precharge operations. Simulation results revealed that the architecture reduces the number of clock cycles for DRAM memory accesses as well as the DRAM power consumption with moderate cost of internal memory. Evaluation of the VLSI implementation of the architecture showed that the throughput of wavelet filtering was increased by parallelizing row filtering with a minimum area cost, thereby enabling DRAM full-page burst accesses to be exploited.

关键词： DWT signal processing parallel architecture efficient memory access burst access ASIC

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A parallel architecture FOR PROBABILISTIC RELAXATION OPERATIONS ON IMAGES

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PATTERN RECOGNITION 1990年第6期23卷 637-645页

作者： CHEN, Z LIN, SY CHEN, YY Department of Computer Science and Information Engineering National Chiao Tung University Hsinchu 30049 Taiwan Republic of China

The design of a parallel architecture for executing probabilistic relaxation operations on two dimensional images is addressed. First of all, the concerned relaxation process is divided into three different parallel operations, i.e. systolic, simultaneous, and pipelined. All these parallel operations are mapped onto a linear array architecture that runs smoothly without any bottleneck in the data flows. The proposed architecture and its components are described. An illustrative running of the relaxation process for an image thresholding application on the architecture is described in some details. The hardware implementation and CAD logic simulation are then given. Finally, performance comparison between the proposed architecture and some existing ones is reported.

关键词： Probabilistic relaxation parallel architecture Linear systolic array Processing element Combiner VLSI chip CAD simulations Performance evaluation

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A parallel architecture FOR RELAXATION OPERATIONS

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PATTERN RECOGNITION 1988年第2期21卷 175-181页

作者： KAMADA, M TORAICHI, K MORI, R YAMAMOTO, K YAMADA, H UNIV TSUKUBA INST INFORMAT SCI & ELECTR1-1 TEN NOUDAISAKURAIBARAKI 305JAPAN UNIV TSUKUBA DOCTORAL PROGRAM ENGNSAKURAIBARAKI 305JAPAN MINIST INT TRADE & IND ELECTROTECH LABSAKURAIBARAKI 305JAPAN

Relaxation method attracts attention as an effective parallel method in image processing and pattern recognition. But their previous parallel implementations are specialized to each application such as image processing at pixel level. The present paper proposes a parallel architecture for a relaxation processor which can be applied to general use. This architecture is based on the round-robin structure of data communication among the processing elements. Its effectiveness is discussed by evaluating its performance when applied to a pattern recognition method.

关键词： Relaxation method parallel architecture Round-robin structure Handwritten character recognition Very large scale integration (VLSI)

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parallel architecture of power-of-two multipliers for FPGAs

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IET CIRCUITS DEVICES & SYSTEMS 2020年第3期14卷 381-389页

作者： Perri, Stefania Spagnolo, Fanny Frustaci, Fabio Corsonello, Pasquale Univ Calabria Dept Mech Energy & Management Engn DIMEG I-87036 Arcavacata Di Rende Italy Univ Calabria Dept Informat Modeling Elect & Syst Engn DIMES I-87036 Arcavacata Di Rende Italy

This research work presents a novel approach to design efficient power-of-two multipliers on modern field-programmable gate arrays (FPGA) devices. Several ways of exploiting fixed-point power-of-two multiplications have been recently demonstrated to reduce the computational complexity of several computationally intensive applications, such as computer vision, deep learning, and many others. Modern FPGA devices provide speed-optimised intellectual property (IP) cores based on embedded modules, such as digital signal processing blocks, and area-optimised IP cores based on reconfigurable logic resources, such as look-up tables and flip-flops. Unfortunately, due either to their limited available amount or to their limited running frequency, these IP cores do not allow the overall computational capability offered by an FPGA device to be completely exploited. While the speed-optimised version of the multiplier proposed here is fast enough to increase the number of operations performed per second by up to 4.3 times, with respect to the conventional designs, its area-optimised implementation reduces resources requirements and energy consumption by up to 22 and 40%.

关键词： flip-flops field programmable gate arrays logic design industrial property circuit optimisation parallel architectures computational complexity embedded systems modern FPGA devices embedded modules digital signal processing blocks area-optimised IP cores reconfigurable logic resources area-optimised implementation parallel architecture modern field-programmable gate arrays fixed-point power-of-two multiplications computational complexity computer vision deep learning power-of-two multiplier design speed-optimised intellectual property cores look-up tables flip-flops IP cores energy consumption

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parallel architecture for generalized LFSR in LSI built-in self testing

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IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 1998年第6期E81A卷 1252-1261页

作者： Matsushima, TK Matsushima, T Hirasawa, S Polytech Univ Dept Informat Engn Sagamihara Kanagawa 2291196 Japan Waseda Univ Sch Sci & Engn Tokyo 1698555 Japan

This paper presents a new architecture for multiple-input signature analyzers. The proposed signature analyzer with H delta inputs is designed by parallelizing a GLFSR(delta, m), where delta is the number of input signals and m is the number of stages in the feedback shift register. The GLFSR, developed by Pradhan and Gupta, is a general framework for representing LFSR-based signature analyzers. The parallelization technique described in this paper can be applied to any kind of GLFSR signature analyzer, e.g., SISRs, MISRs, multiple MISRs and MLFSRs. It is shown that a proposed signature analyzer with H delta inputs requires less complex hardware than either single GLFSR(H delta, m)s or a parallel construction of the H original GLFSR(delta, m)s. It is also shown that the proposed signature analyzer, while requiring simpler hardware, has comparable aliasing probability with analyzers using conventional GLFSRs for some CUT error models of the same test response length and test lime. The proposed technique would be practical for testing CUTs with a large number of output sequences, since the test circuit occupies a smaller area on the LSI chip than the conventional multiple-input signature analyzers of comparable aliasing probability.

关键词： built-in self test signature analysis linear feedback shift register aliasing probability parallel architecture

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parallel architecture to accelerate superparamagnetic clustering algorithm

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ELECTRONICS LETTERS 2020年第14期56卷 701-+页

作者： Wang, Pan Ke Chen, Chang Hao Pun, Sio Hang Zhang, Baijun Mak, Peng Un Vai, Mang I. Lei, Tim C. Univ Macau Inst Microelect State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Univ Macau Dept Elect & Comp Engn Macau Peoples R China Sun Yat Sen Univ Sch Elect & Informat Technol State Key Lab Optoelect Mat & Technol Guangzhou Peoples R China Univ Colorado Dept Elect Engn Denver CO 80202 USA

Superparamagnetic clustering (SPC) is an unsupervised classification technique in which clusters are self-organised based on data density and mutual interaction energy. Traditional SPC algorithm uses the Swendsen-Wang Monte Carlo approximation technique to significantly reduce the search space for reasonable clustering. However, Swendsen-Wang approximation is a Markov process which limits the conventional superparamagnetic technique to process data clustering in a sequential manner. Here the authors propose a parallel approach to replace the conventional appropriation to allow the algorithm to perform clustering in parallel. One synthetic and one open-source dataset were used to validate the accuracy of this parallel approach in which comparable clustering results were obtained as compared to the conventional implementation. The parallel method has an increase of clustering speed at least 8.7 times over the conventional approach, and the larger the sample size, the more increase in speed was observed. This can be explained by the higher degree of parallelism utilised for the increased data points. In addition, a hardware architecture was proposed to implement the parallel superparamagnetic algorithm using digital electronic technologies suitable for rapid or real-time neural spike sorting.

关键词： Monte Carlo methods Markov processes pattern clustering parallel architectures parallel algorithms neurophysiology medical computing Swendsen-Wang Monte Carlo approximation technique Markov process open-source dataset hardware architecture parallel architecture superparamagnetic clustering algorithm unsupervised classification technique data density mutual interaction energy SPC algorithm real-time neural spike sorting digital electronic technology parallel superparamagnetic algorithm

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parallel architecture support for high-speed protocol processing

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MICROPROCESSORS AND MICROSYSTEMS 1997年第6期20卷 325-339页

作者： Chan, TS Gorton, I Computer and Systems Technology Laboratory School of Computer Science and Engineering University of New South Wales Sydney 2052 Australia

A rapid increase in the transmission bandwidth of optical networks has created a bottleneck in protocol processing at the host systems. This paper presents a high-performance transport protocol, HTPNET, that is designed to exploit the evolving characteristics of high-speed networks. Importantly, the highly parallel architecture of HTPNET provides a suitable platform for the parallel implementation of presentation processing, which incurs high computation overheads. A parallel architecture based on the T9000 transputer and C104 router technology has been designed to support high-speed protocol processing. A simulation of the architecture has been implemented and has demonstrated the advantage of exploiting a parallel architecture for protocol processing.

关键词： high-speed networks protocol processing parallel architecture transputer Occam

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parallel architecture FOR HIGH-SPEED VITERBI DECODING OF CONVOLUTIONAL-CODES

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ELECTRONICS LETTERS 1989年第14期25卷 887-888页

作者： ZHANG, YF CSILLAG, P GAPSE/ENDEEIHT Toulouse France

A parallelisation algorithm of decoding convolutional codes with the Viterbi algorithm is presented. The architecture of parallel decoding analysed here suits the VLSI realisation very well and allows high-speed decod... 详细信息

关键词： VLSI VLSI realisation Viterbi algorithm convolutional codes decoding decoding convolutional codes digital integrated circuits high-speed Viterbi decoding high-speed decoding parallel architecture parallel architectures parallelisation algorithm

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