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11th Asia and South Pacific Design Automation Conference

作者： Hwang, Chanseok Pedram, Massoud Univ Southern Calif Dept Elect Engn Syst Los Angeles CA 90089 USA

ISBN: (纸本)0780394518

In this paper, we present a new timing-driven placement algorithm, which attempts to minimize zigzags and crisscrosses on the timing-critical paths of a circuit. We observed that most of the paths that cause timing problems in the circuit meander outside the minimum bounding box of the start and end nodes of the path. To limit this undesirable behavior, we impose a physical constraint on the placement problem, i.e., we assign a preferred signal direction to each critical path in the circuit. Starting from an initial placement solution, by using a move-based optimization strategy, these preferred directions force cells to move in a direction that maximizes the monotonic behavior of the timing-critical paths in the new placement solution. To make the direction assignment tractable, we implicitly group all circuit paths into a set of input-output conduits and assign a unique preferred direction to each such conduit. We integrated this idea into a recursive bipartitioning-based placement framework with a min-cut objective function. Experimental results on a set of standard placement benchmarks show that this approach improves the result of a state-of-the-art industrial placement tool for all the benchmark circuits while increasing the wire length by a tolerable amount.

关键词： circuit CAD integrated circuit design timing benchmark circuits circuit timing-critical paths industrial placement tool input-output conduits min-cut objective function monotone cell ordering constraints move-based optimization strategy recursive biparti circuit CAD integrated circuit design placement Wire length Paths ZIGZAG Byways placement algorithm

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Failure-Aware Application placement Modeling and Optimization in High Turnover DevOps Environment 12

Failure-Aware Application Placement Modeling and Optimizatio...

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12th IEEE International Conference on Cloud Computing (IEEE CLOUD) held as Part of IEEE World Congress on Services (IEEE SERVICES)

作者： Suk, Tonghoon Hwang, Jinho Bulut, Muhammed Fatih Zeng, Zemei IBM TJ Watson Res Ctr New York NY 10598 USA Univ Calif Berkeley Berkeley CA 94720 USA

ISBN: (纸本)9781728127057

DevOps (software DEVelopment and information technology OPerationS) has established a culture and environment, in which building, testing, and releasing software happen more rapidly, frequently, and reliably through automated pipelines. To support this high turnover application cycle, the cluster orchestration frameworks such as Kubernetes or Docker Swarm have evolved to provide high flexibility and reliability. However, while cluster orchestrators run on the cloud infrastructure, any failure incurred from the infrastructure can directly impact the nodes of a cluster, so infrastructure failures can disrupt applications running on the cluster. In this paper, we propose proactive application placement algorithms with prediction of infrastructure failures. The proposed algorithms utilize failure-risk measurements, Failure-Index, determined from turnover rate of applications and prediction of infrastructure failures. We build stochastic models for application turnover and infrastructure failure processes, and provide various types of Failure-Index. Our placement algorithms are implemented in an orchestration framework, Kubernetes, and in the simulation model. Experimental results show that our methods reduce the amount of application disruption by 20% than the state-of-the-art algorithms in Kubernetes.

关键词： DevOps Microservices placement algorithm

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VNF-AAP: Accelerator-aware Virtual Network Function placement

VNF-AAP: Accelerator-aware Virtual Network Function Placemen...

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IEEE Conference on Network Function Virtualization and Software Defined Networks (NFV-SDN)

作者： Sharma, Gourav Prateek Tavernier, Wouter Colle, Didier Pickavet, Mario Univ Ghent IMEC Dept Informat Technol IDLab Ghent Belgium

ISBN: (纸本)9781728145457

Network Function Virtualization aims to migrate packet-processing tasks from special-purpose appliances to Virtual Network Functions (VNFs) running on x86 or ARM servers. However, achieving the line-rate packet-processing for VNFs running on CPUs can be a challenging task. External hardware accelerators can be used to offload heavy-lifting tasks (e.g. en/decryption and hashing) from performance-critical VNFs. State-of-the-art VNF placement algorithms only consider compute resources while assigning VNFs on server nodes. We propose a placement algorithm which takes into consideration hardware accelerator resources in addition to compute resources. For evaluation, we compare the performance of our approach with the Integer Linear Program (ILP) method and also with the state-of-the-art best-fit method of VNF placement.

关键词： NFV hardware accelerator FPGA placement algorithm allocation

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Temporal placement for run-time reconfiguration

Temporal placement for run-time reconfiguration

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19th IEEE Canadian Conference on Electrical and Computer Engineering

作者： Nahas, Carlos Guevara, Ricardo Villalobos Groza, Voicu Univ Ottawa Sch Informat Technol & Engn Ottawa ON K1N 6N5 Canada

ISBN: (纸本)9781424400379

In this paper, we propose the use of an algorithm that will improve the performance of the FPGA placement task for Run-Time Reconfiguration (RTR) computing. Previous literature will be referenced for the sake of presenting related work, as well as to present some algorithms that can be used for the placement of static, compile-time reconfigurable devices. These algorithms will then be examined in order to propose a placement algorithm that will be used in further RTR research.

关键词： run-time reconfiguration placement algorithm

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The Road Less Traveled: Congestion-Aware NoC placement and Packet Routing for FPGAs 34

The Road Less Traveled: Congestion-Aware NoC Placement and P...

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34th International Conference on Field-Programmable Logic and Applications (FPL)

作者： Shahrouz, Soheil Gholami Betz, Vaughn Univ Toronto Dept Elect & Comp Engn Toronto ON Canada

ISBN: (纸本)9798331530082;9798331530075

To help scale to ever-larger and more complex designs, recent FPGA architectures now integrate network-on-chips (NoCs). NoCs help transfer high-bandwidth data over long distances within the chip without using scarce low-delay long routing wire segments. While NoC-enhanced FPGAs aid system integration and design reuse, they also complicate FPGA computer-aided design (CAD) flows by introducing new constraints and metrics. placement and routing needs to optimize NoC metrics like latency and bandwidth utilization and avoid link oversubscription (congestion), while simultaneously optimizing the programmable routing resource usage of the design modules attached to NoC routers. In this work we develop several new approaches to reduce NoC congestion while minimizing the impact on other design metrics. First, we incorporate a NoC link congestion cost into the placement engine of the open-source CAD flow, versatile place & route (VPR). Second, we integrate turn model NoC routing algorithms into the placement engine to leverage path diversity to further reduce congestion. On average over a suite of 29 benchmarks combining placement congestion modeling with turn model packet routing reduces NoC congestion by 90.7% at the cost of increasing aggregate bandwidth demand by 4%. In cases where the enhanced placement engine and NoC routing fail to fully resolve congestion, we formulate NoC routing as a boolean satisfiability (SAT) problem. This approach yields significant additional improvements;the combined algorithm reduces congestion by 95.1% compared to the baseline placement. Finally, we enhance the reinforcement learning (RL) agent in VPR's placement engine by introducing a NoC-aware move type, resulting in an 8.8% reduction in wirelength on designs that make extensive use of the NoC.

关键词： FPGA network-on-chip computer-aided design placement algorithm

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Incremental design methodology for multimillion-gate FPGAs

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JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 2005年第5期14卷 1015-1026页

作者： Ma, J Athanas, P Huang, X Univ New Orleans Dept Elect Engn New Orleans LA 70148 USA Virginia Tech Dept Elect & Comp Engn Blacksburg VA 24060 USA

This paper presents an FPGA design methodology that can be used to shorten the FPGA design-and-debug cycle, especially as the gate counts increase to multimillions. Core-based incremental placement algorithms, in conjunction with fast interactive routing, axe investigated to reduce the design processing time by distinguishing the changes between design iterations and reprocessing only the changed blocks without affecting the remaining part of the design. When combined with a background refinement thread, the incremental approach offers the instant gratification that designers expect, while preserving the fidelity attained through batch-oriented programs. An integrated FPGA design environment is then developed based on the incremental placer and its background refiner. The results show that the incremental design methodology is in orders of magnitude faster than the competing approaches such as the Xilinx M3 tools without sacrificing too much quality.

关键词： incremental techniques placement algorithm JBits APIs design tool core PPGA

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Latency-aware virtual desktops optimization in distributed clouds

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MULTIMEDIA SYSTEMS 2018年第1期24卷 73-94页

作者： Guo, Tian Shenoy, Prashant Ramakrishnan, K. K. Gopalakrishnan, Vijay Worcester Polytech Inst Worcester MA 01609 USA Umass Amherst Amherst MA USA UC Riverside Riverside CA USA AT&T Labs Bedminster NJ USA

Distributed clouds offer a choice of data center locations for providers to host their applications. In this paper, we consider distributed clouds that host virtual desktops which are then accessed by users through remote desktop protocols. Virtual desktops have different levels of latency-sensitivity, primarily determined by the actual applications running and affected by the end users' locations. In the scenario of mobile users, even switching between 3G and WiFi networks affects the latency-sensitivity. We design VMShadow, a system to automatically optimize the location and performance of latency-sensitive VMs in the cloud. VMShadow performs black-box fingerprinting of a VM's network traffic to infer the latency-sensitivity and employs both ILP and greedy heuristic based algorithms to move highly latency-sensitive VMs to cloud sites that are closer to their end users. VMShadow employs a WAN-based live migration and a new network connection migration protocol to ensure that the VM migration and subsequent changes to the VM's network address are transparent to end-users. We implement a prototype of VMShadow in a nested hypervisor and demonstrate its effectiveness for optimizing the performance of VM-based desktops in the cloud. Our experiments on a private as well as the public EC2 cloud show that VMShadow is able to discriminate between latency-sensitive and insensitive desktop VMs and judiciously moves only those that will benefit the most from the migration. For desktop VMs with video activity, VMShadow improves VNC's refresh rate by 90% by migrating virtual desktop to the closer location. Transcontinental remote desktop migrations only take about 4 min and our connection migration proxy imposes 13 mu s overhead per packet.

关键词： Distributed clouds Virtual desktop placement algorithm

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Implementing fine grain processor arrays on field-programmable logic

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INTEGRATED COMPUTER-AIDED ENGINEERING 2000年第1期7卷 53-66页

作者： Vassányi, I Univ Veszprem Dept Informat Syst H-8200 Veszprem Hungary

The structure of Field programmable Gate Arrays (FPGAs) naturally fits that of fine grain array algorithms. The paper investigates the geometrical and layout-related implementation problems of FPGA-based processor arrays. A general methodology for implementing parametrized array processors on FPGAs is presented. Then, a detailed layout algorithm is proposed. A new feature of the algorithm is the uniform treatment of inter- and intra-module nets that allows the layout of the basic processor to be optimized with respect to the critical path of the whole, arbitrarily large processor array. The approach is demonstrated on a massively parallel processor array for binary morphology.

关键词： ARRAY PROCESSORS PROCESSOR massively parallel processors Formal logic Field programmable gate arrays placement algorithm microparticles algorithms layouts

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Corner block list representation and its application to floorplan optimization

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2004年第5期51卷 228-233页

作者： Hong, XL Dong, SQ Huang, G Cai, YC Cheng, CK Gu, J Tsinghua Univ Comp & Sci Dept Beijing 100084 Peoples R China Univ Calif San Diego Dept Comp Sci & Engn La Jolla CA 92110 USA Hong Kong Univ Sci & Technol Dept Comp Sci Hong Kong Hong Kong Peoples R China

We propose to use a corner block list (CBL) representation for mosaic floorplans. In a mosaic floorplan, each room has only one block assigned to it. Thus, there is a unique corner room on the to p right corner of the chip. Corner block deletion and corner block insertion keep the floorplan mosaic. Through a recursive deletion process, a mosaic floorplan can be converted to a representation that is named as CBL. Given a CBL, it takes only linear time to construct the floorplan. The CBL is used for the application to very large-scale integration floorplan and building block placement. We adopt a simulated annealing process for the optimization. Soft blocks and the aspect ratio of the chip are taken into account in the optimization process. The experimental results demonstrate that the algorithm is quite promising.

关键词： building block layout floorplanning representation NP hard placement algorithm simulated annealing

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Multi-Objective MDP-Based Routing in UAV Networks for Search-Based Operations

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IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY 2024年第9期73卷 13777-13789页

作者： Mahajan, Prateek Palanisamy, Balamurugan Kumar, Anusha Chalapathi, G. S. S. Chamola, Vinay Khabbaz, Maurice Birla Inst Technol & Sci BITS Pilani Dept Elect & Elect Engn EEE Pilani 333031 India Amer Univ Beirut Comp Sci Dept 11-0236-CMPS Beirut Lebanon

Unmanned aerial vehicle (UAV) systems have gained widespread recognition due to their versatility and autonomy. Their deployment for disaster mitigation and management operations is seen as one of their most important applications over the past decade. In such UAV networks, routing plays a crucial role in determining network performance parameters such as network lifetime, data transmission latency, and packet delivery ratio. This paper presents a novel routing mechanism - Multi-Objective Markov Decision Based Routing (MOBMDP) for UAV networks carrying out search-based operations. MOBMDP models routing decisions in a Markov Decision Process (MDP) framework and uses Q-learning to take decisions. It compares routing paths using three metrics, viz., Remaining Energy of the Minimum Energy Node (REMEN), Power Distance ratio (PD), and Expected Delay (ED). Amongst these metrics, PD is a novel metric proposed by this work. PD simultaneously optimizes the energy efficiency and energy distribution in the network. Further, MOBMDP uses a novel reinforcement learning inspired method to estimate transmission delay in a given path. Intensive simulation studies compare MOBMDP to four state-of-the-art routing protocols. Results show a significant improvement in network lifetime, packet delivery ratio, energy efficiency, average data transmission delay, and error in delay estimation.

关键词： Routing Delays Autonomous aerial vehicles Prediction algorithms Q-learning Routing protocols Measurement UAV search and rescue placement algorithm routing protocol network lifetime network coverage transmission delay estimation energy efficiency

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