检索结果-内蒙古大学图书馆

100 Gb/s All-Optical programmable logic array Chip Based on Full Set of Canonical logic Units

100 Gb/s All-Optical Programmable Logic Array Chip Based on ...

2023 Asia Communications and Photonics Conference/2023 International Photonics and Optoelectronics Meetings, ACP/POEM 2023

作者： Gao, Xiaoyan Gu, Wentao Dong, Wenchan Xu, Jing Dong, Jianji Zhang, Xinliang Huazhong University of Science and Technology Wuhan National Laboratory for Optoelectronics Wuhan China Huazhong University of Science and Technology School of Optical and Electronic Information Wuhan China

We experimentally demonstrate an all-optical programmable logic array scheme through linear pre-coding and nonlinear four-wave mixing in silicon-based integrated chip. The full set of canonical logic units are generat... 详细信息

ISBN: (纸本)9798350312614

关键词： all-optical signal processing optical computing programmable logic array silicon photonics

来源：评论

学校读者我要写书评

暂无评论

Large-scale optical programmable logic array for two-dimensional cellular automaton

引用

Advanced Photonics 2024年第5期6卷 104-113页

作者： Wenkai Zhang Bo Wu Wentao Gu Junwei Cheng Hailong Zhou Dongmei Huang Ping-kong Alexander Wai Liao Chen Wenchan Dong Jianji Dong Xinliang Zhang Huazhong University of Science and Technology Wuhan National Laboratory for OptoelectronicsSchool of Optical and Electronic InformationWuhanChina The Hong Kong Polytechnic University Shenzhen Research Institute ShenzhenChina The Hong Kong Polytechnic University Photonics Research InstituteDepartment of Electrical and Electronic EngineeringHong KongChina Hong Kong Baptist University Department of PhysicsHong KongChina

Despite more than 40 years of development,it remains difficult for optical logic computing to support more than four operands because the high parallelism of light has not been fully exploited in current methods that are restrained by inefficient optical nonlinearity and redundant input *** this paper,we propose a large-scale optical programmable logic array(PLA)based on parallel spectrum *** fully exploiting the wavelength resource,an eight-input PLA is experimentally demonstrated with 256 wavelength *** it is extended to nine-input PLA through the combination of wavelength’s and spatial *** on PLA,many advanced logic functions like 8-256 decoder,4-bit comparator,adder and multiplier,and state machines are first realized in *** implement the two-dimensional optical cellular automaton(CA)for what we believe is the first time and run Conway’s Game of Life to simulate the complex evolutionary processes(pulsar explosion,glider gun,and breeder).Other CA models,such as the replicator-like evolution and the nonisotropic evolution to generate the Sierpinski triangle are also *** work significantly alleviates the challenge of scalability in optical logic devices and provides a universal optical computing platform for two-dimensional CA.

关键词： optical computing programmable logic array optical cellular automaton

来源：评论

学校读者我要写书评

暂无评论

A NEW APPROACH TO programmable logic array FOR SINGLE-CLOCK CMOS

引用

Journal of Electronics(China) 2006年第1期23卷 157-160页

作者： Yin Yongsheng Liu Cong Gao Minglun Institute of VLSI Design Hefei University of Technology Hefei 230009 China Institute of VLSI Design Nanjing University Nanjing 510093 China

programmable logic array (PLA) is an important building circuit of VLSI chips and some of the FPGA architectures have evolved from the basic PLA architectures. In this letter, a dynamic and static mixed PLA with single-phased clock is presented. Combining both dynamic and static design style rather than introducing additional interface-buffers overcomes the racing problem, thereby saves the chip area. Besides inheriting the advantages of dynamic circuit-low power dissipation and compact structure, this approach also provides high-speed operation.

关键词： programmable logic array Single clock Dynamic Static Mixed circuit

来源：评论

学校读者我要写书评

暂无评论

MULTIPLE-VALUED DECOMPOSITION OF GENERALIZED BOOLEAN FUNCTIONS AND THE COMPLEXITY OF programmable logic-arrayS

引用

IEEE TRANSACTIONS ON COMPUTERS 1981年第9期30卷 635-643页

作者： SASAO, T Department of Electrical Engineering Osaka University Abstract Authors References Cited By Keywords Metrics Similar Download Citation Email Print Request Permissions

Generalized Boolean functions are shown to be useful for the design of programmable logic arrays (PLA"s), and the complexity of three types of PLA"s is obtained by the theory of multiple- valued decomposition. A two-level PLA consists of an AND array and an OR array, and they are cascaded to perform a two-level AND-OR circuit. A PLA with decoders consists of decoders, an AND array, and an OR array. A three-level PLA consists of a D array, an AND array, and an OR array, and they are cascaded to perform a three-level OR- AND-OR circuit. It is shown that a generalized Boolean function f(X1, X2,··, Xr):X Bni → B, where B = {0,1}, is represented by a generalized Boolean expression of 2ni-valued variables Xi; and f can be directly realized by a PLA with decoders or a three-level PLA. To realize a function of n-variables (n = 2r), the following sizes are shown to be sufficient: for a two-level PLA, (n + ½) 2n; for a PLA with two-bit decoders, 4(n + 4) 2n; for a three-level PLA, 2n+ (3n + l)√2n+ 2n2Especially in the case of PLA with two-bit decoders, the following sizes are shown to be necessary and sufficient: for an arbitrary symmetric function, 3/2(n + ½) √3n; and for a parity function, (n + ½)√ 2n.

关键词： Complexity of logic circuits functional decomposition multiple-valued logic programmable logic array symmetric function

来源：评论

学校读者我要写书评

暂无评论

logic DESIGN OF programmable logic-arrayS

引用

IEEE TRANSACTIONS ON COMPUTERS 1979年第9期28卷 609-617页

作者： KAMBAYASHI, Y KYOTO UNIV DEPT INFORMAT SCIKYOTO 606JAPAN

Compared with random logic circuits, memory-type circuits are more suitable for LSI realization since their iterated structure of identical cells results in higher transistor density and higher yield. A programmable logic array (PLA) is a read only memory (ROM) with programmable addresses and it is suitable for realizing logic functions with many unspecified input combinations. For such a function, reduction of the number of input is possible in many cases. Since the cost of a PLA is mainly determined by the number of pins and the chip, both of which are affected by the number of inputs, the reduction of the number of inputs is very important in PLA design. On the other hand, the reduction of the number of product terms in a sum-of-product expression is important in conventional random logic synthesis. Since there is a tradeoff problem between the number of inputs and the number of product terms, we give a design procedure by the following preference order: 1) minimizing the number of pins, 2) minimizing the number of product terms, 3) minimizing the number of circuits used in the PLA. These factors also determine the area required for a chip.

关键词： Incompletely specified logic function logic design multiple-output function programmable logic array reduction of the number of inputs two-level circuit

来源：评论

学校读者我要写书评

暂无评论

A function-independent self-test for large programmable logic arrays

引用

Integration, the VLSI Journal 1983年第1期1卷 71-80页

作者： Grassl, G. Pfleiderer, H.-J. Siemens AG Research Laboratories D-8000 München 83 Germany

It has been shown that small PLAs can be made self-testing. The proposed methods however fail to handle large functions fast or result in a large overhead. Here a method is shown that can be implemented efficiently at large PLAs. The test only needs a system clock and an initialization signal, producing a go/no-go signal after an AND plane size-dependent delay. © 1983.

关键词： programmable logic array Self-test signature analysis

来源：评论

学校读者我要写书评

暂无评论

All-Optical programmable logic arrays Using SOA-Based Canonical logic Units

All-Optical Programmable Logic Arrays Using SOA-Based Canoni...

引用

Conference on Information Optics and Optical Data Storage II

作者： Lei, Lei Dong, Jianji Yu, Yu Zhang, Xinliang Huazhong Univ Sci & Technol Wuhan Natl Lab Optoelect Wuhan 430074 Peoples R China

ISBN: (纸本)9780819493149

All-optical programmable logic arrays (PLAs) based on canonical logic units (CLUs), i.e. minterms and maxterms, are presented. We experimentally demonstrated the full set of two-input and three-input minterms as well as maxterms using the cross-gain modulation in semiconductor optical amplifiers (SOAs). Maxterms can be easily obtained based on minterms. The reconfigurability and scalability of the system are largely enhanced compared to our previous work. Correct and clear temporal waveforms are achieved for all the canonical logic units. The measured extinction ratios of two-input and three-input CLUs are similar to 15 dB and similar to 11 dB, respectively. Four important logic functions, including multiplier, multiplexer, demultiplexer and decoder, are presented as examples to show that the canonical logic units-based programmable logic array (CLUs-PLA) can be reconfigured to perform different logic functions.

关键词： Optical signal processing optical computing optical logic devices nonlinear optics semiconductor optical amplifier programmable logic array

来源：评论

学校读者我要写书评

暂无评论

The OR-k method for on-line checking of programmable logic arrays

引用

Journal of Electronic Testing 1992年第1期3卷 53-65页

作者： Marcynuk, D.M. Miller, D.M. Department of Computer Science University of Manitoba Winnipeg R3T 2N2 MB Canada Department of Computer Science University of Victoria Victoria V8W 3P6 B.C. Canada

A programmable logic array (PLA) is nonconcurrent if every input pattern selects exactly one product term. We relax this requirement to limited concurrency where all product terms selected by the same input pattern must have identical output parts. A new testing method, OR-k testability, is developed for the on-line (concurrent) checking of limited concurrency PLAs. OR-k testing detects errors due to the selection of one or more extra product terms, and a conventional two-rail parity check on the outputs detects the other errors from single stuck-at, bridging, cross-point and broken line faults. The output patterns of an OR-k testable PLA must be unordered. For such PLAs, certain subsets of the outputs take on an all 1's pattern only in the presence of an extra product term error condition. A limited concurrency PLA tested by OR-k testability is strongly fault secure. © 1992 Kluwer Academic Publishers.

关键词： concurrency fault secure design on-line checking programmable logic array

来源：评论

学校读者我要写书评

暂无评论

Design of multiple-valued programmable logic arrays

Design of multiple-valued programmable logic arrays

引用

作者： Yong Ha Ko NAVAL POSTGRADUATE SCHOOL

学位级别：硕士

The goal of this thesis is the development of a programmable logic array (PLA) that accepts multiple-valued inputs and produces multiple valued outputs. The PLA is implemented in CMOS and multiple levels are encoded as current. It is programmed by choosing transistor geometries which control the current level at which the PLA reacts to inputs. An example of a 4-valued PLA is shown. As part of this research, a C program was written that produces a PLA layout.

关键词： Multiple-Valued logic Function programmable logic array Circuit Generation Simulation

来源：评论

学校读者我要写书评

暂无评论

ABOUT FOLDED-PLA AREA AND FOLDING EVALUATION

引用

INTEGRATION-THE VLSI JOURNAL 1987年第3-4期5卷 193-215页

作者： CAVIGLIA, DD PIURI, V SANTOMAURO, M POLITECN MILAN DEPT ELECTRI-20133 MILANITALY UNIV BRESCIA DEPT IND AUTOMATBRESCIAITALY

This paper deals with PLA folding strategies: in particular, the accurate evaluation of the area used by folded PLA's is presented. Criteria are proposed to choose the best folding strategy among those considered,... 详细信息

关键词： programmable logic array folding strategies folding evaluation

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：