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A 6-bit segmented dac Architecture With up to 56-GHz Sampling Clock and 6-V_pp Differential Swing

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES 2016年第3期64卷 881-891页

作者： Balteanu, Andreea Schvan, Peter Voinigescu, Sorin P. Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 3G4 Canada Ciena Corp Ottawa ON K2K 3C8 Canada

A distributed power digital-to-analog converter (dac) architecture with multi-level segmentation is proposed. Due to its large output voltage swing, it can be used as a large swing arbitrary waveform generator suitable for a variety of wireline, fiber optic, and instrumentation applications. A proof-of-concept 56-GS/s 6-bit implementation with most significant bits (MSBs) and least significant bits (LSBs) segmentation and full-rate clock was manufactured in a production 130-nm SiGe BiCMOS technology. The circuit features 14 independent data bits-seven for the three MSBs and seven for the three LSBs-each running at up to at least 44 Gb/s. The measured saturated output power and bandwidth are 17 dBm and 45 GHz, respectively. An output swing of 3.4 V-pp per side is observed in 50-Omega loads. Spectral measurements demonstrate multi-bit modulation at carrier frequencies as high as 56 GHz. To the best of our knowledge, this marks the highest output-bandwidth highest voltage-swing current-steering dac in silicon.

关键词： Current steering digital-to-analog converter (dac) distributed amplifiers (DAs) power dac segmented dac SiGe BiCMOS

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A 1-V, 10-bit, 250 MS/s, Current-Steering segmented dac for Video Applications 20

A 1-V, 10-bit, 250 MS/s, Current-Steering Segmented DAC for ...

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20th IEEE-Computer-Society Annual Symposium on VLSI (ISVLSI)

作者： Kumar, Shiv Chandra Siddharth, R. K. Kumar, Nithin Y. B. Vasantha, M. H. Natl Inst Technol Goa Dept Elect & Commun Engn Ponda Goa India

ISBN: (纸本)9781665439466

This paper presents a 10-bit current-steering digital-to-analog converter (CS-dac) in a 45-nm CMOS process with a supply voltage of 1 V. This architecture is based on the segmentation of binary and unary dac architectures for least significant bits (LSBs) and most significant bits (MSBs) respectively. Thus, the circuit consists of an architecture of 9 bit CS-dac comprising a 3-bit binary weighted and 6-bit unary weighted dac. Keeping the power constraints approximately same as 9-bit architecture, a 10-bit architecture is designed in this work using a switched capacitor network cascaded with the 9-bit dac. The proposed architecture is able to reduce the power dissipation by 50% (approximately). A capacitor, C-Bucket is used to store the output from the 9-bit dac architecture, which is used to generate the final output voltage corresponding to the 10-bit resolution. The proposed design operates with a sampling rate of 250 MHz. The architecture consumes a power of 4 mW with an effective number of bits (ENOB) of 9.44 bits. Also, the design achieves spurious free dynamic range of 70 dB.

关键词： Current Cell Unary weighted Binary weighted segmented dac Row/Column Decoder

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A 10-bit 500 MSPS segmented dac with Optimized Current Sources to Avoid Mismatch Effect

A 10-bit 500 MSPS Segmented DAC with Optimized Current Sourc...

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IEEE-Computer-Society Annual Symposium on VLSI (ISVLSI)

作者： Sarkar, Santanu Banerjee, Swapna Natl Inst Technol Dept ECE Rourkela Rourkela India Indian Inst Technol Dept E & ECE Kharagpur 721302 W Bengal India

ISBN: (纸本)9781479987191

This paper describes the design techniques of a segmented current steering (CS) digital-to-analog converter (dac) with optimum sizing of the current sources. The dac has been designed in 0.18 mu m CMOS n-well technology provided by National Semiconductor. The 10-bit dac is segmented as 5+5, where the 5-LSB bits are implemented in binary and the 5-MSB bits are implemented in unary architecture. The matching of the unit current sources plays an important role in determining the overall linearity of the dac. Static linearity of the dac can be improved by using larger area of the current source transistors, sacrificing the dynamic performances. At high frequency the spectral performance of the dac degrades due to the increased parasitic. In this work the current sources are designed with optimum sizes to achieve improved static as well as dynamic performances. In simulation, the dac achieves a maximum DNL of 0.248 LSB and a maximum INL of 0.440 LSB. The dac achieves a maximum spurious free dynamic range (SFDR) of 59.79 dB for 5.37 MHz signal in mismatch environment at 500 MSPS sampling rate. The dac shows a Nyquist SFDR of 57 dB at 500 MSPS sampling rate with mismatch. The dac consumes only 17.85 mW of power for Nyquist signal at 500 MSPS sampling rate with 1.8 V supply.

关键词： Current steering dac segmented dac Matching INL DNL Low Power SFDR Nyquist Signal Frequency

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An 8-Bit 4x4 segmented Current-Steering dac for Bipolar Biphasic Stimulators 65

An 8-Bit 4x4 Segmented Current-Steering DAC for Bipolar Biph...

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IEEE 65th International Midwest Symposium on Circuits and Systems (MWSCAS)

作者： De Aguirre, Paulo Cesar C. Da Fonseca, Fabio D. Girardi, Alessandro G. Fed Univ Pampa Comp Architecture & Microelect Grp Alegrete Brazil

ISBN: (纸本)9781665402798

The use of electrical stimulation is being demonstrated effective for the treatment of human motor disorders. The miniaturization of implantable stimulators demands the development of programmable systems in order to control the amount of injected charge for a given therapy. It requires the generation of biphasic pulses with different current amplitudes. The dac is an important module in this system. dac linearity is a key aspect, since current amplitudes must be accurately controlled by a digital input code. This work describes the development of a current-steering 8-bit segmented dac followed by a power output stage for a bipolar stimulator capable to generate current levels from -255 mu A to +255 mu A with resolution of 1 mu A in 180 nm process technology. Post-layout results demonstrated a maximum DNL and INL of 0.1685 and 1.71 LSBs, respectively.

关键词： stimulator segmented dac current source biomedical

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A 10-bit segmented M-string dac

A 10-bit Segmented <i>M</i>-string DAC

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IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (ElConRus)

作者： Yenuchenko, Mikhail S. Pilipko, Mikhail M. Morozov, Dmitry V. Peter Great St Petersburg Polytech Univ St Petersburg Russia

A 10-bit digital-to-analog converter is presented. It is implemented by segmented architecture with identical weighting elements arrays. Weighting elements and switches have a unified implementation based on transmiss... 详细信息

ISBN: (纸本)9781538643402

关键词： digital-to-analog converter R-string dac segmented dac systematic error compensation

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Maximizing the Resolution of SAR ADC With Multisegmented dac Using Improved MLE Calibration

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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT 2023年 72卷

作者： Huang, Jiajie Chen, Yinuo Zhou, Ting Lu, Wangzilu Lu, Yewangqing Zhao, Jian Li, Yongfu Shanghai Jiao Tong Univ Dept Micronano Elect Shanghai 200240 Peoples R China Shanghai Jiao Tong Univ MoE Key Lab Artificial Intelligence Shanghai 200240 Peoples R China Univ Washington Seattle WA 98195 USA

Successive approximation register analog to digital converters (SAR ADCs) offer an attractive energy-efficient solution but its signal-to-noise-distortion-ratio (SNDR) is degraded due to its sensitivity to parasitic capacitance and capacitors' mismatch. In this article, we present an improved maximum likelihood estimation (MLE) algorithm, which offers a more robust estimator for statistical-based calibration technique that can be used across different resolutions of SAR ADC. The result has demonstrated that our proposed algorithm has further improved the SNDR up to 5.86 dB for a 12-20-bit SAR ADC with multisegmented digital-to-analog converter (dac) compared to state-of-the-art algorithms.

关键词： Registers Calibration Analog-digital conversion Maximum likelihood estimation Capacitors Voltage Quantization (signal) Analog-to-digital converter (ADC) digital-to-analog converter (dac) segmented dac statistical-based calibration successive approximation register (SAR)

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A 16 Channel High-Voltage Driver with 14 Bit Resolution for Driving Piezoelectric Actuators

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2015年第7期62卷 1726-1736页

作者： Pierco, Ramses Torfs, Guy Verbrugghe, Jochen Bakeroot, Benoit Bauwelinck, Johan Univ Ghent INTEC Imec IMinds Dept Informat Technol B-9000 Ghent Belgium Univ Ghent IMEC Ctr Microsyst Technol CMST B-9052 Ghent Belgium

A high-voltage, 16 channel driver with a maximum voltage of 72 volt and 14 bit resolution in a high-voltage CMOS (HV-CMOS) process is presented. This design incorporates a 14 bit monotonic by design dac together with a high-voltage complementary class AB output stage for each channel. All 16 channels are used for driving a piezoelectric actuator within the control loop of a micropositioning system. Since the output voltages are static most of the time, a class AB amplifier is used, implementing voltage feedback to achieve 14 bit accuracy. The output driver consists of a push-pull stage with a built-in output current limitation and high-impedance mode. Also a protection circuit is added which limits the internal current when the output voltage saturates against the high-voltage rail. The 14 bit resolution of each channel is generated with a segmented resistor string dac which assures monotonic by design behavior by using leapfrogging of the buffers used between segments. A diagonal shuffle layout is used for the resistor strings leading to cancellation of first order process gradients. The dense integration of 16 channels with high peak currents results in crosstalk, countered in this design by using staggered switching and resampling of the output voltages.

关键词： High-voltage driver HV-CMOS monotonic by design piezoelectric actuators segmented dac

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A 10-bit 1.8 V 45 mW 100 MHz CMOS transmitter chip for use in an XDSL modem in a home network

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ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING 2014年第2期81卷 515-527页

作者： Sung, Guo-Ming Chou, Wen-Duen Yu, Chih-Ping Natl Taipei Univ Technol Dept Elect Engn Taipei 10608 Taiwan Natl Sci Council Div Engn & Appl Sci Taipei Taiwan Natl Taipei Univ Technol Res & Dev Ctr Taipei 10608 Taiwan Alpha Imaging Technol Corp Analog Design Div Hsinchu Taiwan

This paper describes a 10-bit 1.8 V 45 mW 100 MHz transmitter chip (TX chip) that is fabricated using 0.18 mu m 1P6 M CMOS technology for use in an xDSL modem in a home network. The chip is composed of a 10-bit segmented digital-to-analog converter (dac) and a fully differential adaptive line driver (LD). In designing the dac, the switched-current method is used to increase the conversion speed;the anti-process-variation current cell with threshold-voltage compensation is used to reduce the linearity error, and the current cell, with differential input and gain boosting, is used to minimize the feedthrough error and tapered error distribution. The circuit layout of the current source has four-phase symmetry, not only to increase the linearity but also to eliminate the gradient error. To design a fully differential adaptive LD, the feed-forward capacitor and quiescent current control circuit are used to reduce the zero-crossing distortion and to minimize the second-order harmonic. Additionally, the power efficiency is increased using an output-impedance matching circuit. Measurements reveal that, for a TX chip at a differential load of 100 Omega and a supplied voltage of 1.8 V, the efficient number of bits, operating frequency, output voltage, output current, power consumption, differential nonlinearity error and integral nonlinearity error are 9 bits, 100 MHz, +/- A 0.874 V, +/- A 10 mA, 45.8 mW, -0.80 to +0.62 LSB, and -0.92 to +0.82 LSB, respectively.

关键词： segmented dac xDSL Adaptive line driver Transmitter chip Analog front end (AFE) Home network

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Understanding High-Resolution Dynamic Element Matching dacs [Feature]

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IEEE CIRCUITS AND SYSTEMS MAGAZINE 2023年第4期23卷 34-43页

作者： Alvarez-Fontecilla, Enrique Wilkins, Paul S. Rose, Steven C. Analog Devices Inc San Diego CA 92128 USA Analog Devices Inc Wilmington MA 01887 USA

DEM in the context of non-segmented dacs is well understood in general, and numerous articles can be found in the literature on this topic and its fundamentals. DEM in the context of segmented dacs is a more puzzling subject, as randomizing the mismatch-induced error of a dac whose elements are nominally different in size is not straightforward. In this article, we cover the topic of segmented DEM dacs via the step-bystep derivation of a simple dac architecture that is linear by virtue of its shuffling scheme.

关键词： Circuits and systems Digital-analog conversion Turning High-resolution imaging Digital-to-analog converter (dac) dither dynamic element matching (DEM) segmented dac shuffling quantization

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A 10-bit current-steering CMOS digital to analog converter

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AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS 2015年第1期69卷 14-17页

作者： Yi, Shu-Chung Natl Changhua Univ Educ Dept Comp Sci & Informat Engn Changhua 500 Taiwan Asia Univ Dept Comp Sci & Informat Engn Taichung 41354 Taiwan

This paper proposed a 10-bit digital-to-analog converter consisting of a segmented current-steering architecture, with five different sizes of current source. The proposed 10-bit digital-to-analog converter was implemented using TSMC CMOS 0.35 mu m 2P4M technology. The power consumption was approximately 7.9 mW at the sample rate of 200 MHz, and the supply voltage was 3.3 V. It achieved a DNL (differential nonlinearity) and an INL (integral nonlinearity) of 0.16 LSB and 0.13 LSB, respectively. The measured SFDR (spurious free dynamic range) was 45.3 dB under a 1 MHz sine waveform. This work presented a good performance compared with other researches in DNL, INL and power consumption. (C) 2014 Elsevier GmbH. All rights reserved.

关键词： Current-steering dac Digital to analog converter DNL INL segmented dac

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