This paper presents the design considerations and implementation of a novel topology digital multistage-noise-shaping （MASH） delta-sigma modulator suitable for fractional-N phase-locked-loop （PLL） frequency synthe...
详细信息
This paper presents the design considerations and implementation of a novel topology digital multistage-noise-shaping （MASH） delta-sigma modulator suitable for fractional-N phase-locked-loop （PLL） frequency synthesis. In an effort to reduce the complexity and dissipation,a pipeline technique has been used, and the proposed carry save tree （CST） algorithm optimizes the multi-input adder structure. The circuit has been verified through Matlab simulation, ASIC implementation, and FPGA experiment, which exhibits high performance and potential for a gigahertz range,low-power monolithic CMOS frequency synthesizer.
有界模型校验(Bounded Model Checking)由于验证的不完备性而经常受到验证人员的指责。为了解决这个问题,计算时序深度的算法被提出。该文算法基于可满足性算法引擎,与其它基于可满足性算法引擎的算法不同,为了减少可满足性算法引擎的负...
详细信息
有界模型校验(Bounded Model Checking)由于验证的不完备性而经常受到验证人员的指责。为了解决这个问题,计算时序深度的算法被提出。该文算法基于可满足性算法引擎,与其它基于可满足性算法引擎的算法不同,为了减少可满足性算法引擎的负担,采用了状态空间显式存储的方法。ISCAS’89的实例很好证明了该算法的有效性。
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