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Discovering Cohesive Temporal Subgraphs with Temporal Density Aware Exploration

Journal of Computer Science & Technology 2022年第5期37卷 1068-1085页

作者： Chun-Xue Zhu Long-Long Lin Ping-Peng Yuan Hai Jin National Engineering Research Center for Big Data Technology and System Huazhong University of Science and TechnologyWuhan 430074China Service Computing Technology and System Laboratory Huazhong University of Science and TechnologyWuhan 430074China Cluster and Grid Computing Laboratory Huazhong University of Science and TechnologyWuhan 430074China School of Computer Science and Technology Huazhong University of Science and TechnologyWuhan 430074China

Real-world networks,such as social networks,cryptocurrency networks,and e-commerce networks,always have occurrence time of interactions between *** networks are typically modeled as temporal *** cohesive subgraphs from temporal graphs is practical and essential in numerous data mining applications,since mining cohesive subgraphs gets insights into the time-varying nature of temporal ***,existing studies on mining cohesive subgraphs,such as Densest-Exact and k-truss,are mainly tailored for static graphs(whose edges have no temporal information).Therefore,those cohesive subgraph models cannot indicate both the temporal and the structural characteristics of *** this end,we explore the model of cohesive temporal subgraphs by incorporating both the evolving and the structural characteristics of temporal ***,the volume of time intervals in a temporal network is *** a result,the time complexity of mining temporal cohesive subgraphs is *** efficiently address the problem,we first mine the temporal density distribution of temporal *** by the distribution,we can safely prune many unqualified time intervals with the linear time ***,the remaining time intervals where cohesive temporal subgraphs fall in are examined using the greedy *** results of the experiments on nine real-world temporal graphs indicate that our model outperforms state-of-the-art solutions in efficiency and ***,our model only takes less than two minutes on a million-vertex DBLP and has the highest overall average ranking in EDB and TC metrics.

关键词： temporal network temporal feature distribution cohesive subgraph convex property

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A 155 Mbps laser diode driver with automatic power and extinction ratio control

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Journal of Zhejiang University-Science A(Applied Physics & Engineering) 2007年第8期8卷 1346-1350页

作者： CHEN Xiao-fei ZOU Xue-cheng LIN Shuang-xi LIU Zheng-lin JIN Hai Department of Electronic Science and Technology Huazhong University of Science and Technology Wuhan 430074 China School of Electric and lnformation Engineering Wuhan Institute of Technology Wuhan 430073 China Cluster and Grid Computing Laboratory Huazhong University of Science and Technology Wuhan 430074 China

An integrated laser diode driver(LDD) driving an edge-emitting laser diode was designed and fabricated by 0.35 μm BiCMOS technology. This paper proposes a scheme which combines the automatic power control loop and temperature com-pensation for modulation current in order to maintain constant extinction ratio and average optical power. To implement tem-perature compensation for modulation current,a novel circuit which generates a PTAT current by using the injecting base current of a bipolar transistor in saturation region,and alternates the amplifier feedback loop(closed or not) to control the state of the current path is presented. Simulation results showed that programmed by choice of external resistors,the IC can provide modu-lation current from 5 mA to 85 mA with temperature compensation adjustments and independent bias current from 4 mA to 100 mA. Optical test results showed that clear eye-diagrams can be obtained at 155 Mbps,with the output optical power being nearly constant,and the variation of extinction ratio being lower than 0.7 dB.

关键词： Laser diode driver （LDD） Automatic power control （APC） Extinction ratio Temperature compensation

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A Survey on Graph Processing Accelerators:Challenges and Opportunities

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Journal of Computer Science & Technology 2019年第2期34卷 339-371页

作者： Chuang-Yi Gui Long Zheng Bingsheng He Cheng Liu Xin-Yu Chen Xiao-Fei Liao Hai Jin National Engineering Research Center for Big Data Technology and System School of Computer Science and Technology Huazhong University of Science and Technology Wuhan 430074 China Services Computing Technology and System Laboratory School of Computer Science and Technology Huazhong University of Science and Technology Wuhan 430074 China Cluster and Grid Computing Laboratory School of Computer Science and Technology Huazhong University of Science and Technology Wuhan 430074 China School of Computing National University of Singapore Singapore 117418 Singapore Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China

Graph is a well known data structure to represent the associated relationships in a variety of applications,e.g.,data science and machine *** a wealth of existing efforts on developing graph processing systems for improving the performance and/or energy efficiency on traditional architectures,dedicated hardware solutions,also referred to as graph processing accelerators,are essential and emerging to provide the benefits significantly beyond what those pure software solutions can *** this paper,we conduct a systematical survey regarding the design and implementation of graph processing ***,we review the relevant techniques in three core components toward a graph processing accelerator:preprocessing,parallel graph computation,and runtime *** also examine the benchmarks and results in existing studies for evaluating a graph processing ***,we find that there is not an absolute winner for all three aspects in graph acceleration due to the diverse characteristics of graph processing and the complexity of hardware *** finally present and discuss several challenges in details,and further explore the opportunities for the future research.

关键词： graph processing accelerator domain-specific architecture performance energy efficiency

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Minimal Context-Switching Data Race Detection with Dataflow Tracking

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Journal of Computer Science & Technology 2024年第1期39卷 211-226页

作者：郑龙李洋辛杰刘海峰郑然廖小飞金海 National Engineering Research Center for Big Data Technology and System School of Computer Science and Technology Huazhong University of Science and TechnologyWuhan 430074China Services Computing Technology and System Laboratory School of Computer Science and TechnologyHuazhong University of Science and TechnologyWuhan 430074China Cluster and Grid Computing Laboratory School of Computer Science and TechnologyHuazhong University of Science and TechnologyWuhan 430074China

Data race is one of the most important concurrent anomalies in multi-threaded *** con-straint-based techniques are leveraged into race detection,which is able to find all the races that can be found by any oth-er sound race ***,this constraint-based approach has serious limitations on helping programmers analyze and understand data ***,it may report a large number of false positives due to the unrecognized dataflow propa-gation of the ***,it recommends a wide range of thread context switches to schedule the reported race(in-cluding the false one)whenever this race is exposed during the constraint-solving *** ad hoc recommendation imposes too many context switches,which complicates the data race *** address these two limitations in the state-of-the-art constraint-based race detection,this paper proposes DFTracker,an improved constraint-based race detec-tor to recommend each data race with minimal thread context ***,we reduce the false positives by ana-lyzing and tracking the dataflow in the *** this means,DFTracker thus reduces the unnecessary analysis of false race *** further propose a novel algorithm to recommend an effective race schedule with minimal thread con-text switches for each data *** experimental results on the real applications demonstrate that 1)without removing any true data race,DFTracker effectively prunes false positives by 68%in comparison with the state-of-the-art constraint-based race detector;2)DFTracker recommends as low as 2.6-8.3(4.7 on average)thread context switches per data race in the real world,which is 81.6%fewer context switches per data race than the state-of-the-art constraint based race ***,DFTracker can be used as an effective tool to understand the data race for programmers.

关键词： data race satisfiability modulo theory multi-threaded program dynamic detection

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FDGLib: A Communication Library for Efficient Large-Scale Graph Processing in FPGA-Accelerated Data Centers

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Journal of Computer Science & Technology 2021年第5期36卷 1051-1070页

作者： Yu-Wei Wu Qing-Gang Wang Long Zheng Xiao-Fei Liao Hai Jin Wen-Bin Jiang Ran Zheng Kan Hu National Engineering Research Center for Big Data Technology and System School of Computer Science and Technology Huazhong University of Science and TechnologyWuhan 430074China Services Computing Technology and System Laboratory School of Computer Science and Technology Huazhong University of Science and TechnologyWuhan 430074China Cluster and Grid Computing Laboratory School of Computer Science and TechnologyHuazhong University of Science and TechnologyWuhan 430074China

With the rapid growth of real-world graphs,the size of which can easily exceed the on-chip(board)storage capacity of an accelerator,processing large-scale graphs on a single Field Programmable Gate Array(FPGA)becomes *** multi-FPGA acceleration is of great necessity and *** cloud providers(e.g.,Amazon,Microsoft,and Baidu)now expose FPGAs to users in their data centers,providing opportunities to accelerate large-scale graph *** this paper,we present a communication library,called FDGLib,which can easily scale out any existing single FPGA-based graph accelerator to a distributed version in a data center,with minimal hardware engineering *** provides six APIs that can be easily used and integrated into any FPGA-based graph accelerator with only a few lines of code *** the torus-based FPGA interconnection in data centers,FDGLib also improves communication efficiency using simple yet effective torus-friendly graph partition and placement *** interface FDGLib into AccuGraph,a state-of-the-art graph *** results on a 32-node Microsoft Catapult-like data center show that the distributed AccuGraph can be 2.32x and 4.77x faster than a state-of-the-art distributed FPGA-based graph accelerator ForeGraph and a distributed CPU-based graph system Gemini,with better scalability.

关键词： data center accelerator graph processing distributed architecture communication optimization

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Massively parallel algorithms for fully dynamic all-pairs shortest paths

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Frontiers of Computer Science 2024年第4期18卷 201-203页

作者： Chilei WANG Qiang-Sheng HUA Hai JIN Chaodong ZHENG National Engineering Research Center for Big Data Technology and System Services Computing Technology and System LabCluster and Grid Computing LabSchool of Computer Science and TechnologyHuazhong University of Science and TechnologyWuhan 430074China State Key Laboratory for Novel Software Technology Nanjing UniversityNanjing 210023China

1 Introduction In recent years,the Massively Parallel Computation(MPC)model has gained significant ***,most of distributed and parallel graph algorithms in the MPC model are designed for static graphs[1].In fact,the graphs in the real world are constantly *** size of the real-time changes in these graphs is smaller and more *** graph algorithms[2,3]can deal with graph changes more efficiently[4]than the corresponding static graph ***,most studies on dynamic graph algorithms are limited to the single machine ***,a few parallel dynamic graph algorithms(such as the graph connectivity)in the MPC model[5]have been proposed and shown superiority over their parallel static counterparts.

关键词： dynamic shortest gained

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Towards High-Performance Graph Processing: From a Hardware/Software Co-Design Perspective

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Journal of Computer Science & Technology 2024年第2期39卷 245-266页

作者：廖小飞赵文举金海姚鹏程黄禹王庆刚赵进郑龙张宇邵志远 National Engineering Research Center for Big Data Technology and System School of Computer Science and Technology Huazhong University of Science and TechnologyWuhan 430074China Services Computing Technology and System Laboratory School of Computer Science and Technology Huazhong University of Science and TechnologyWuhan 430074China Cluster and Grid Computing Laboratory School of Computer Science and TechnologyHuazhong University of Science and TechnologyWuhan 430074China Zhejiang Lab Hangzhou 311121China

Graph processing has been widely used in many scenarios,from scientific computing to artificial *** processing exhibits irregular computational parallelism and random memory accesses,unlike traditional ***,running graph processing workloads on conventional architectures(e.g.,CPUs and GPUs)often shows a significantly low compute-memory ratio with few performance benefits,which can be,in many cases,even slower than a specialized single-thread graph *** domain-specific hardware designs are essential for graph processing,it is still challenging to transform the hardware capability to performance boost without coupled software *** article presents a graph processing ecosystem from hardware to *** start by introducing a series of hardware accelerators as the foundation of this ***,the codesigned parallel graph systems and their distributed techniques are presented to support graph ***,we introduce our efforts on novel graph applications and hardware *** results show that various graph applications can be efficiently accelerated in this graph processing ecosystem.

关键词： graph processing hardware accelerator software system high performance ecosystem

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P3DC:Reducing DRAM Cache Hit Latency by Hybrid Mappings

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Journal of Computer Science & Technology 2024年第6期39卷 1341-1360页

作者： Ye Chi Ren-Tong Guo Xiao-Fei Liao Hai-Kun Liu Jianhui Yue National Engineering Research Center for Big Data Technology and System Wuhan 430074China Services Computing Technology and System Laboratory Wuhan 430074China Cluster and Grid Computing Laboratory Wuhan 430074China School of Computer Science and Technology Huazhong University of Science and TechnologyWuhan 430074China School of Big Data and Internet Shenzhen Technology UniversityShenzhen 518118China Department of Computer Science Michigan Technological UniversityHoughton 49931-1295U.S.A.

Die-stacked dynamic random access memory(DRAM)caches are increasingly advocated to bridge the performance gap between the on-chip cache and the main *** fully realize their potential,it is essential to improve DRAM cache hit rate and lower its cache hit *** order to take advantage of the high hit-rate of set-association and the low hit latency of direct-mapping at the same time,we propose a partial direct-mapped die-stacked DRAM cache called *** design is motivated by a key observation,i.e.,applying a unified mapping policy to different types of blocks cannot achieve a high cache hit rate and low hit latency *** address this problem,P3DC classifies data blocks into leading blocks and following blocks,and places them at static positions and dynamic positions,respectively,in a unified set-associative *** also propose a replacement policy to balance the miss penalty and the temporal locality of different *** addition,P3DC provides a policy to mitigate cache thrashing due to block type *** results demonstrate that P3DC can reduce the cache hit latency by 20.5%while achieving a similar cache hit rate compared with typical set-associative caches.P3DC improves the instructions per cycle(IPC)by up to 66%(12%on average)compared with the state-of-the-art direct-mapped cache—BEAR,and by up to 19%(6%on average)compared with the tag-data decoupled set-associative cache—DEC-A8.

关键词： die-stacked dynamic random access memory(DRAM) cache set-associative direct-mapped hit latency

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One-Sided Message Passing Programming Model for Unstructured Peer-to-Peer computing System

One-Sided Message Passing Programming Model for Unstructured...

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IEEE International Conference on Computer and Information Technology Workshops, CIT

作者： Hai Jin Fei Luo Qin Zhang Xiaofei Liao Hao Zhang Services Computing Technology and System Laboratory Cluster and Grid Computing Laboratory Huazhong University of Science and Technology Wuhan China Services Computing Technology and System Laboratory Cluster and Grid Computing Laboratory Huazhong University of Science and Technology Wuhan China

The programming is still a challenging issue for the high performance distributed computing (HPDC) platform, and it is critical to the popularity of peer-to-peer (P2P) based HPDC systems. Therefore, this paper focuses on the design and implementation of OMP, a one-sided message passing programming model for unstructured P2P computing system, P2HP. Based on taskspsila execution flow, P2HP provides a one-sided point-to-point message-passing communication library, and a software development kit with rich APIs for applicationspsila parallelization. Furthermore, a serial sequence alignment algorithm is parallelized with OMP in P2HP. The evaluation shows that OMP makes P2HP practical and efficient.

关键词： Message passing Peer to peer computing Application software Parallel programming Distributed computing Software libraries grid computing Computer architecture Concurrent computing High performance computing

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grid and Cooperative computing - GCC 2004 Workshops 1

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丛书名： Lecture Notes in Computer Science

1000年

作者： Hai Jin Yi Pan Nong Xiao Jianhua Sun

ISBN: (数字)9783540302070

ISBN: (纸本)9783540235781

Welcome to the proceedings of GCC2004 and the city of Wuhan. grid computing has become a mainstream research area in computer science and the GCC conference has become one of the premier forums for presentation of new and exciting research in all aspectsofgridandcooperativecomputing. Theprogramcommitteeispleasedtopresent the proceedings of the 3rd International Conference on grid and Cooperative Comp- ing (GCC2004), which comprises a collection of excellent technical papers, posters, workshops, and keynote speeches. The papers accepted cover a wide range of exciting topics, including resource grid and service grid, information grid and knowledge grid, grid monitoring,managementand organizationtools, grid portal, grid service, Web s- vices and their QoS, service orchestration, grid middleware and toolkits, software glue technologies, grid security, innovative grid applications, advanced resource reservation andscheduling,performanceevaluationandmodeling,computer-supportedcooperative work, P2P computing, automatic computing, and meta-information management. The conference continues to grow and this year a record total of 581 manuscripts (including workshop submissions) were submitted for consideration. Expecting this growth, the size of the program committee was increased from 50 members for GCC 2003 for 70 in GCC 2004. Relevant differences from previous editions of the conf- ence: it is worth mentioning a signi?cant increase in the number of papers submitted by authors from outside China; and the acceptance rate was much lower than for p- vious GCC conferences. From the 427 papers submitted to the main conference, the program committee selected only 96 regular papers for oral presentation and 62 short papers for poster presentation in the program.

关键词： Theory of Computation Computer Communication Networks Operating Systems Information Systems Applications (incl. Internet) Information Storage and Retrieval User Interfaces and Human Computer Interaction

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