In this pivotal study, we delve into the imperative realm of Diabetic Retinopathy (DR), a sight-threatening eye disease, introducing a nuanced and comprehensive approach to its detection through cutting-edge deep lear...
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Vaccination strategy is crucial in fighting the COVID-19 pandemic. Since the supply is still limited in many countries, contact network-based interventions can be most powerful to set an efficient strategy by identify...
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This paper presents ChestBox, a novel approach that utilizes state functions to facilitate low-latency state sharing for stateful serverless computing. When an application function needs to share a state, the state fu...
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Edge learning (EL) is an end-to-edge collaborative learning paradigm enabling devices to participate in model training and data analysis, opening countless opportunities for edge intelligence. As a promising EL framew...
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This paper establishes requirements for assessing the usability of Explainable Artificial Intelligence (XAI) methods, focusing on non-AI experts like healthcare professionals. Through a synthesis of literature and emp...
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The scheduling of final exams at a university is a problem which can be improved with artificial intelligence techniques. In this paper we explain and compare two algorithms used to solve the exam scheduling problem a...
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Die-stacked dynamic random access memory(DRAM)caches are increasingly advocated to bridge the performance gap between the on-chip cache and the main *** fully realize their potential,it is essential to improve DRAM ca...
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Die-stacked dynamic random access memory(DRAM)caches are increasingly advocated to bridge the performance gap between the on-chip cache and the main *** fully realize their potential,it is essential to improve DRAM cache hit rate and lower its cache hit *** order to take advantage of the high hit-rate of set-association and the low hit latency of direct-mapping at the same time,we propose a partial direct-mapped die-stacked DRAM cache called *** design is motivated by a key observation,i.e.,applying a unified mapping policy to different types of blocks cannot achieve a high cache hit rate and low hit latency *** address this problem,P3DC classifies data blocks into leading blocks and following blocks,and places them at static positions and dynamic positions,respectively,in a unified set-associative *** also propose a replacement policy to balance the miss penalty and the temporal locality of different *** addition,P3DC provides a policy to mitigate cache thrashing due to block type *** results demonstrate that P3DC can reduce the cache hit latency by 20.5%while achieving a similar cache hit rate compared with typical set-associative caches.P3DC improves the instructions per cycle(IPC)by up to 66%(12%on average)compared with the state-of-the-art direct-mapped cache—BEAR,and by up to 19%(6%on average)compared with the tag-data decoupled set-associative cache—DEC-A8.
We study decentralized federated learning (DFL) in edge computing networks where edge nodes (ENs) collaboratively train their artificial intelligence (AI) models in a serverless manner without sharing local data. We c...
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This research investigates the application of deep learning techniques to sentiment analysis, a field focused on mining online platforms for subjective assessments. By combining deep neural networks (DNNs) with partic...
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Lightweight cryptography aims to design secure and efficient cryptographic algorithms for resource-constrained devices. Traditional cryptographic algorithms may not be readily usable in resource-constrained environmen...
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