This paper presents a rigorous field theory analysis of the slow-wave propagation characteristics on semiconductor based coplanar waveguide MIS transmission lines with ion-implantation doping profile by using the freq...
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This paper presents a rigorous field theory analysis of the slow-wave propagation characteristics on semiconductor based coplanar waveguide MIS transmission lines with ion-implantation doping profile by using the frequency-domain TLM method (FDTLM). Two types of coplanar MIS transmission line structures, namely bulk silicon and semiconductor-on-insulator (SOI) with a Gaussian profile of the doping depth and optimized lateral width of the doping region have been investigated. It was found that both structures exhibit much better slow-wave characteristics at lower losses than traditional thin-film MIS transmission lines.
In this paper we have laid the foundations for a functional test generation procedure based on a cyclomatic complexity measure (CCM) and on the reduced, ordered binary decision diagram representation (ROBDD) for Boole...
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In this paper we have laid the foundations for a functional test generation procedure based on a cyclomatic complexity measure (CCM) and on the reduced, ordered binary decision diagram representation (ROBDD) for Boolean function manipulation, The CCM has been defined for single-output and multioutput electronic circuits. This measure computes the number of BDD paths to be transformed into test vectors. This new test generation approach, failed CYCLOGEN, has been implemented, and the tests for several functional primitives, as well as the ISCAS-85 benchmark circuits, have been generated successfully. The results show that this approach is effective and promising.
This paper presents a detailed experimental investigation of gate current limitation effects on power GaAs FET's rf performances. This limitation is accomplished entirely by dynamic compensation of the gate bias v...
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This paper presents a detailed experimental investigation of gate current limitation effects on power GaAs FET's rf performances. This limitation is accomplished entirely by dynamic compensation of the gate bias voltage. Effects of this current limitation on power added efficiency and output power performances have been examined through an extensive experimental investigation using active second-harmonic loading over the entire Smith chart, Comprehensive results are given and enable the determination of the optimal gate resistor value needed in the de path for gate current limitation, Thermal runaway problem is also considered when selecting the gate resistor. The current limitation mechanism is analyzed in the case where the gate voltage is controlled in a feedback loop for linearization purposes. Measurements performed on a feedback linearized amplifier are presented and show the behavior of the gate current and its effects on intermodulation product levels.
This paper describes a novel noise parameter measurement technique using a nonrepeatable and uncalibrated mechanical stub tuner and a built-in reverse six-port reflectometer. The main advantages of this approach are: ...
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This paper describes a novel noise parameter measurement technique using a nonrepeatable and uncalibrated mechanical stub tuner and a built-in reverse six-port reflectometer. The main advantages of this approach are: 1) avoiding the use of an automated repeatable mechanical tuner or thermally controlled electronic tuner, 2) the noise and S-parameter characterization of the tuner is not required, 3) the convenience to change the measurement reference plane, without need of further tuner calibration, and 4) the relatively low cost of the test set, compared to a commercial system. Measurements are obtained for the NE 76184 general-purpose GaAs FET and compared to the noise figure calculated using the data provided by the manufacturer for different source impedance values.
This paper presents a novel, nonconventional family of converters for low-voltage, high-current applications based on a peculiar series connection of the primary windings. On the secondary side, all the semiconductors...
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This paper presents a novel, nonconventional family of converters for low-voltage, high-current applications based on a peculiar series connection of the primary windings. On the secondary side, all the semiconductors are directly connected in parallel without resorting to the use of interphase transformers or any other current sharing means. The series connection of the primaries ensures current sharing while zigzag arrangement provides the desired pulse number.
This paper presents a new empirical DC model which includes self-heating effects, The expression of the collector current does not explicitly incorporate the junction temperature of the device to aid convergence proce...
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This paper presents a new empirical DC model which includes self-heating effects, The expression of the collector current does not explicitly incorporate the junction temperature of the device to aid convergence process and to simplify the equations involved, A comparison of simulated and experimental DC-IV characteristics over the ohmic and active regions demonstrates the accuracy of the model, This model is suitable for optimization purposes and has been implemented in nonlinear circuit simulators, HSPICE and HP-MDS.
A systematic scaling approach for the modeling of high-power/large-size HBT's is presented, This approach is based on: 1) identifying and characterizing the elementary cell, and 2) modeling the input/output interc...
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A systematic scaling approach for the modeling of high-power/large-size HBT's is presented, This approach is based on: 1) identifying and characterizing the elementary cell, and 2) modeling the input/output interconnections using the device's physical layout. The proposed approach reduces the optimization problem for the large-size device to the easier fitting of the lumped equivalent circuit of the elementary cell, It is shown that there is a good agreement between the predicted results, using the developed model, and the available measurements for different bias points, Such a modeling approach is particularly appealing for high-power applications where the large-signal characterization of large-size devices becomes a difficult task, particularly for on-wafer devices,
This paper presents a new approach for generating test vectors for combinational circuits. In the approach presented here, the automatic test generator, called BDD FTEST, uses an algebraic method to find a set of test...
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This paper presents a new approach for generating test vectors for combinational circuits. In the approach presented here, the automatic test generator, called BDD FTEST, uses an algebraic method to find a set of test vectors for single stuck lines. For all the circuits analyzed, the algorithm is faster than previously algebraic methods. Experimental results demonstrate that, for most circuits, our algorithm can generate test vectors for all faults in a very short time, particularly for large circuits like the c7552.
Punctured convolutional codes allow an easy implementation of variable-rate encoders/decoders. In this paper, the puncturing technique is used to generate new QAM trellis codes from a rate-1/2 code. These codes are tr...
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Punctured convolutional codes allow an easy implementation of variable-rate encoders/decoders. In this paper, the puncturing technique is used to generate new QAM trellis codes from a rate-1/2 code. These codes are true high-rate codes, without parallel branches in the trellis. A simplified decoding technique is also presented. It is shown that the advantages the puncturing technique provides with binary convolutional codes are essentially maintained with trellis-coded modulation.
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