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14-Bit SAR ADC with on-Chip Digital Bubble Sorting Calibration technology

Chinese Journal of Electronics 2025年第1期34卷 125-136页

作者： Hua Fan Zhuorui Chen Tongrui Xu Franco Maloberti Qi Wei Quanyuan Feng School of Integrated Circuit Science and Engineering(Exemplary School of Microelectronics) University of Electronic Science and Technology of China Shenzhen Institute for Advanced Study University of Electronic Science and Technology of China Chongqing Institute of Microelectronics Industry Technology University of Electronic Science and Technology of China Department of Electrical Computer and Biomedical Engineering University of Pavia Department of Precision Instrument Tsinghua University Institute of Microelectronics Southwest Jiaotong University

This article designs a 14-bit successive approximation register analog-to-digital converter（SAR ADC）.A novel digital bubble sorting calibration method is proposed and applied to eliminate the effect of capacitor mismatch on the linearity of the SAR ADC. To reduce the number of capacitors, a hybrid architecture of a high 8-bit binary-weighted capacitor array and a low 6-bit resistor array is adopted by the digital-to-analog（DAC）. The common-mode voltage VCM-based switching scheme is chosen to reduce the switching energy and area of the DAC. The time-domain comparator is employed to obtain lower power consumption. Sampling is performed through a gate voltage bootstrapped switch to reduce the nonlinear errors introduced when sampling the input signal. Moreover, the SAR logic and the whole calibration is totally implemented on-chip through digital integrated circuit（IC） tools such as design compiler, IC compiler, etc. Finally, a prototype is designed and implemented using 0.18 μm bipolar-complementary metal oxide semiconductor（CMOS）-double-diffused MOS 1.8 V CMOS technology. The measurement results show that the SAR ADC with on-chip bubble sorting calibration method achieves the signal-to-noise-and-distortion ratio of 69.75 dB and the spurious-free dynamic range of 83.77 dB.

关键词： Semiconductor device measurement Capacitors Linearity Switches Calibration System-on-chip Frequency measurement Time-domain analysis Sorting Signal to noise ratio

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Strong ferroelectric and luminescence properties of 0-3 type 0.8BaTiO_(3)-0.2CaTiO_(3):Pr^(3+)composite ceramics prepared by cold sintering process

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Journal of Advanced Ceramics 2024年第7期13卷 1002-1010页

作者： Xiaocui Rao Xueling Yang Renbing Sun Peng Du Hai Jiang Yao Huang Laihui Luo Department of Microelectronics Science and Engineering School of Physical Science and TechnologyNingbo UniversityNingbo 315211China College of Materials Science and Engineering Ningbo University of TechnologyNingbo 315016China

0-3 type ferroelectric-phosphor composite ceramics cannot be prepared by the traditional solid-state sintering(SSS)method due to the strong chemical reaction between ferroelectrics and phosphors during high-temperature *** cold sintering process(CSP)may solve this issue by densifying ceramics at ultralow sintering *** this work,dense 0-3 type 0.8BaTiO_(3)-0.2CaTiO_(3):Pr^(3+)(0.8BT-0.2CT:Pr^(3+))binary composite ceramics were fabricated at an ultralow temperature of 225℃via CSP with the Ba(OH)2·8H2O hydrated *** effects of the Ba(OH)_(2)·8H2O content,sintering temperature,and sintering time on the microstructure and densification of the ceramics were *** density of the composite ceramics prepared by the optimized sintering parameters reaches 89%.Both energy-dispersive X-ray(EDX)spectroscopy and X-ray diffraction(XRD)confirm the existence of BT and CT:Pr^(3+)phases in the prepared ceramics.A strong ferroelectric performance is obtained,and the luminescent properties of CT:Pr^(3+)are preserved for the ***,the 0.8BT-0.2CT:Pr^(3+)composite ceramics prepared by CSP have stronger photoluminescence and photo-stimulated luminescence than their counterparts prepared by cold sintering assistance(CSA)and SSS ***,CSP is a promising method for combining luminescent and ferroelectric properties into 0-3 type composite ceramics.

关键词： single-step densification cold sintering composite ceramics ferroelectric luminescence

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Apparatus for producing single strontium atoms in an optical tweezer array

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Chinese Physics B 2024年第12期33卷 100-105页

作者： Kai Wen Huijin Chen Xu Yan Zejian Ren Chengdong He Elnur Hajiyev Preston Tsz Fung Wong Gyu-Boong Jo Microelectronics Thrust The Hong Kong University of Science and Technology(Guangzhou)Guangzhou 511455China Department of Physics The Hong Kong University of Science and TechnologyHong Kong 999077China

We outline an experimental setup for efficiently preparing a tweezer array of^(88)Sr *** setup uses permanent magnets to maintain a steady-state two-dimensional magneto-optical trap(MOT)which results in a loading rate of up to10^(8)s^(-1)at 5 mK for the three-dimensional blue *** enables us to trap 2×10^(6)^(88)Sr atoms at 2μK in a narrow-line red MOT with the^(1)S_(0)→^(3)P_(1)intercombination transition at 689 *** the Sisyphus cooling and pairwise loss processes,single atoms are trapped and imaged in 813 nm optical tweezers,exhibiting a lifetime of 2.5 *** further investigate the survival fraction of a single atom in the tweezers and characterize the optical tweezer array using a release and recapture *** experimental setup serves as an excellent reference for those engaged in experiments involving optical tweezer arrays,cold atom systems,and similar research.

关键词： optical tweezer array single atom sisyphus cooling

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A grid-connected eleven-level power conversion interface

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International Journal of Electronics 2025年第5期112卷 949-967页

作者： Wu, Jinn-Chang Chen, Fu-Zen Jou, Hurng-Liahng Chen, Yi-Ting Department of Microelectronics Engineering National Kaohsiung University of Science and Technology Kaohsiung Taiwan Department of Electrical Engineering National Kaohsiung University of Science and Technology Kaohsiung Taiwan

This paper proposes a grid-connected eleven-level power conversion interface (GCELPCI) for renewable power systems. The proposed GCELPCI is composed of a four-port DC-DC power converter (FPDDPC) and an eleven-level inverter (ELI). The FPDDPC combines a boost power converter and a transformer with a turn ratio of 2:1 to generate multiple combinations of the output voltages for the DC bus voltage of the ELI. The ELI integrates an asymmetric voltage technique on a T-type inverter to further convert the DC output voltages of FPDDPC into eleven-level AC voltage. A sinusoidal current is generated by the proposed GCELPCI through the filter inductor and injected into the power grid. Only nine power electronic switches are used in the ELI to generate an eleven-level AC voltage, the number of power electronic switches is reduced to simplify the power circuit. In addition, the capacity of the filter inductor is reduced. A digital signal processor (DSP) and a complex programmable logic device (CPLD) chip are used as the digital controller to complete a hardware prototype to verify the performance of the proposed GCELI. © 2024 Informa UK Limited, trading as Taylor & Francis Group.

关键词： Digital signal processors

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Sintering Driven Void Formation in PS@WO3 Core-shell Composites: A Photodegradation Enhancement Strategy

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Current Analytical Chemistry 2024年第8期20卷 557-568页

作者： Yeh, Min Yen You, Ruei Ying Cheng, Po Wen Hwang, Shih-Syuan Hu, Gui-Cheng Chang, Shun Hsyung Department of Microelectronics Engineering National Kaohsiung University of Science and Technology Kaohsiung81157 Taiwan

Background: Polystyrene nanospheres are used as a substrate for the hydrothermal coating of tungsten trioxide (WO3) to form a core-shell composite of PS@WO3. The core-shell structure is used for the next sintering step. This produces porous WO3. The focus of this study is on the role of porous WO3 in enhancing photocatalytic performance. Methods: The hydrothermal method was employed for coating, and the surface morphology, as well as the structural properties of WO3-coated PS spheres, were systematically investigated using SEM and XRD analyses. Additionally, the sintering process was introduced to enhance the material by inducing rupture in the PS sphere core, creating voids that significantly increased the material's surface area. Results: The evaluation of the effect of sintering temperature on photodegradation efficiency highlighted the crucial role of sintering temperature. Un-sintered and 300°C sintered WO3, both having a hexagonal crystalline structure, exhibited superior degradation efficiencies compared to samples sintered at higher temperatures (400°C and 500°C). In particular, the 300°C sintered WO3 outperformed its un-sintered counterpart despite identical crystalline structures. The performance of the PS@WO3 composite was assessed to determine the enhanced role of porous WO3. The porous WO3 obtained, in particular by the sintering of the core-shell PS@WO3 composites at 300°C, showed a remarkable improvement in the degradation efficiency. These composite demonstrated over 95% efficiency within 10 minutes and achieved near complete (100%) degradation for a further 10 minutes, surpassing the performance of pure WO3. It is important to clarify that while the final product was predominantly WO3 after the sintering process, the inclusion of PS served a critical purpose in creating voids during sintering. The PS@WO3 composite structure used as a resource for the preparation of porous WO3, even with a potentially reduced PS composition, has been found to play a

关键词： Tungsten compounds

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Seven-level dual-buck inverter for photovoltaic power generation

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IET Renewable Power Generation 2024年第12期18卷 1880-1892页

作者： Wu, Jinn-Chang Jou, Hurng-Liahng Chen, Fu-Zen Huang, Han-Xin Department of Microelectronics Engineering National Kaohsiung University of Science and Technology Kaohsiung Taiwan Department of Electrical Engineering National Kaohsiung University of Science and Technology Kaohsiung Taiwan

A power processing system (PPS) with a seven-level dual-buck inverter (SLDBI) for a photovoltaic (PV) power generation system is proposed. The PPS is comprised of a boost power converter and an SLDBI. The boost power converter matches the voltage of the PV array with that of the SLDBI and functions as the maximum power point tracker for the PV array. The SLDBI consists of a dual-buck bridge converter (DBBC) and a three-level DC converter (TLDC). The DBBC effectively reduces leakage current in the PPS and prevents current from flowing through the parallel body diode of the power switches, allowing the use of MOSFETs as power electronic switches to enhance power efficiency. The TLDC is structured as a semi-controlled full-bridge system to generate a three-level DC voltage. Besides, the DBBC and TLDC produce a seven-level AC voltage and drive a sinusoidal current to the utility. The SLDBI reduces both the filter inductor size and the switching loss of power switches. With only six power switches, it simplifies the power circuit. A hardware prototype has been built to experimentally verify the proposed PPS. © 2024 The Author(s). IET Renewable Power Generation published by John Wiley & Sons Ltd on behalf of The Institution of Engineering and technology.

关键词： Buck converter

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Capturing Head Poses Using FMCW Radar and Deep Neural Networks

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IEEE Transactions on Aerospace and Electronic Systems 2025年第3期61卷 6748-6759页

作者： Kumchaiseemak, Nakorn Fioranelli, Francesco Wilaiprasitporn, Theerawit Vidyasirimedhi Institute of Science and Technology Rayong21210 Thailand Group Department of Microelectronics Delft2628 CD Netherlands

This article presents the first subject-specific head pose estimation approach using only one frequency-modulated continuous wave radar data frame. Specifically, the proposed method incorporates a deep learning framework to estimate head pose rotation and orientation frame-by-frame by combining a convolutional neural network operating on range-angle radar plots and a PeakConv network. The proposed method is validated with an in-house collected dataset, including annotated head movements that varied in roll, pitch, and yaw, and these were recorded in two different indoor environments. It is shown that the proposed model can estimate head poses with a relatively small error of approximately 6.7°–14.4° for all rotational axes and is capable of generalizing to unseen, new environments when trained in one scenario (e.g., lab) and tested in another (e.g., office), including in the cabin of a car. © 1965-2011 IEEE.

关键词： Convolutional neural networks

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An Online Maximum Efficiency Point Tracking Technique for Bidirectional Noninverting Buck-Boost Converter over Wide Power Range

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IEEE Transactions on Power Electronics 2024年第7期39卷 7995-8006页

作者： Chen, Fu-Zen Jou, Hurng-Liahng Wu, Jinn-Chang Hung, Hao-Che Luo, Jun-Yao National Kaohsiung University of Science and Technology Department of Electrical Engineering Kaohsiung80778 Taiwan National Kaohsiung University of Science and Technology Department of Microelectronics Engineering Kaohsiung81157 Taiwan

This article presents a novel approach for online tracking of the maximum efficiency point of a bidirectional noninverting buck-boost converter over a wide range of power levels. The proposed technique involves perturbing the phase shift of the gate driver signal and observing the input power and output power to maximize efficiency within both the zero-voltage switching quadrangle mode and the hard switching quadrangle mode. To achieve two modes of operation, a zero-voltage switching detecting circuit is built. This circuit helps detect whether the switching achieves zero voltage switching, sets the phase shift boundary, and adjusts dead time. To evaluate the effectiveness of the proposed approach, a 500 W hardware prototype has been developed. © 1986-2012 IEEE.

关键词： Buck-Boost converter

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Task-Level Parallelism for the Multifrontal Method in Tightly Coupled CPU-FPGA Architectures

Task-Level Parallelism for the Multifrontal Method in Tightl...

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2024 IEEE High Performance Extreme Computing Conference, HPEC 2024

作者： He, Zerong Cheng, Zekang Xu, Zhongguang Jin, Xi Institute of Microelectronics Department of Physics University of Science and Technology of China China School of Microelectronics University of Science and Technology of China China

ISBN: (纸本)9798350387131

The multifrontal method is an efficient direct method for solving sparse linear systems. This algorithm transforms the factorization of a large and sparse matrix into a sequence of dense matrix operations. Some of these dense operations can be accelerated with FPGAs, while others are suitable for CPUs. In this paper, we propose a tightly coupled heterogeneous domain-specific architecture (DSA) for the efficient execution of the multifrontal algorithm. This tightly coupled hardware architecture ensures low communication overhead between the CPU and FPGA. Each matrix operation is assigned to the CPU or FPGA based on its characteristics. Furthermore, we apply the task-based scheduling model for multi-core architectures to our heterogeneous DSA. Considering the difference in the storage structure of the CPU and FPGA, we modify the original task graph and propose a data-centric task graph that is more suitable for the FPGA. Based on this scheduling model, we propose two optimizations to further improve performance. Finally, we test the scheduling overhead of the system and determine the finest task granularity accordingly. We evaluate our architecture on Xilinx ZCU102. Compared to MUMPS, for a set of 5 matrices, our implementation can achieve an average of 4.3 × performance improvement with just 10 % of the computing power. © 2024 IEEE.

关键词： Matrix factorization

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Observation of memristive behavior in PDMS-glass nanofluidic chip

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Nano Research 2025年第2期18卷 725-732页

作者： Weiling Sun Yike Xiao Pingyuan Yan Fei Sun Xuan Zhang Chuanxiang Sheng Qi Wang Yefeng Yu School of Microelectronics Nanjing University of Science and TechnologyNanjing 210094China Key Laboratory of New Membrane Materials Ministry of Industry and Information TechnologySchool of Environmental and Biological EngineeringNanjing University of Science and TechnologyNanjing 210094China Department of Optical Science and Engineering School of Information Science and TechnologyFudan UniversityShanghai 200433China

Nanofluidic memristors,which use ions in electrolyte solutions as carriers,have been developed rapidly and brought new opportunities for the development of neuromorphic *** the transport and accumulation of ions in nanochannels to process information is an endeavor to realize the nanofluidic *** this study,we report a new nanofluidic memristor,which is a polydimethylsiloxane(PDMS)-glass chip with two platinum(Pt)electrodes and well-aligned multi-nanochannels within PDMS for ion enrichment and *** device not only exhibits typical bipolar memristive behavior and ion current rectification(ICR)but also demonstrates excellent endurance,maintaining stable performance after 100 sweep *** systematically investigate the key factors affecting ion transport behavior in this *** results show that the ICR ratio of the current-voltage(I-V)hysteresis curves decreases with increasing scan rate and solution *** potential measurements are introduced to reveal that the PDMS surface carries more negative charges in higher pH solutions,resulting in more pronounced memristive and ICR ***,our memristor can simulate short-term synaptic plasticity,such as paired-pulse facilitation(PPF)and paired-pulse depression(PPD),with a relatively low energy consumption of 12 pJ per spike per ***,the inherent accessibility and robustness of our nanofluidic memristors facilitate the optimization of device structure and *** important observations and investigations lay a foundation for advancing energy-saving and efficient neuromorphic computing.

关键词： polydimethylsiloxane(PDMS)-glass chip nanofluidic memristor nanochannel short-term synaptic plasticity(STP)

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